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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bus32_big_tb.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
wishbone
wb_uart16550
bus32_big_tb
 
 
 
 
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
   
    
      destination
      top.bus32_big_tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 

 
 
 


    UART_MODEL_CLKCNT4'b1100
    UART_MODEL_SIZE4

 
 
 
       
 
 
              
              Params
 
              
                
                                   spirit:library="wishbone"
                                   spirit:name="wb_uart16550"
                                   spirit:version="bus32_big_dut.params"/>
 
 
 
 
             
              
 
 
              
              Bfm
 
              
                                   spirit:library="wishbone"
                                   spirit:name="wb_uart16550"
                                   spirit:version="bfm.design"/>
              
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              headersheaders
 
              Verilog
              
              
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 
 
 

 
 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
    
 
 
 
    
      fs-sim
 
      
        
        ../verilog/common/top.bus32_big_tb
        verilogSourcemodule
      
 
    
 
 
    
      fs-lint
 
      
        
        ../verilog/common/top.bus32_big_tb
        verilogSourcemodule
      
 
 
 
    
 
 
 
  
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`wishbone`
39			`wb_uart16550`
40			`bus32_big_tb`
41
42
43
44
45
46
47
48
49
50
51
52
53
54			`gen_verilog`
55			`104.0`
56			`none`
57			`common`
58			`./tools/verilog/gen_verilog`
59
60
61			`destination`
62			`top.bus32_big_tb`
63
64
65			`dest_dir`
66			`../verilog`
67
68
69			`top`
70
71
72
73
74
75
76
77
78
79
80
81
82			`UART_MODEL_CLKCNT4'b1100`
83			`UART_MODEL_SIZE4`
84
85
86
87
88
89
90
91
92			`Params`
93
94
95
96			`spirit:library="wishbone"`
97			`spirit:name="wb_uart16550"`
98			`spirit:version="bus32_big_dut.params"/>`
99
100
101
102
103
104
105
106
107
108			`Bfm`
109
110
111			`spirit:library="wishbone"`
112			`spirit:name="wb_uart16550"`
113			`spirit:version="bfm.design"/>`
114
115
116
117
118			`icarus`
119
120
121			`spirit:library="Testbench"`
122			`spirit:name="toolflow"`
123			`spirit:version="icarus"/>`
124
125
126
127
128
129
130
131			`headersheaders`
132
133			`Verilog`
134
135
136
137
138			`commoncommon`
139
140			`Verilog`
141
142
143			`fs-common`
144
145
146
147
148
149
150			`sim:Simulation:`
151
152			`Verilog`
153
154
155			`fs-sim`
156
157
158
159
160			`lint:Lint:`
161			`Verilog`
162
163
164			`fs-lint`
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183			`fs-common`
184
185
186
187			`../verilog/tb.ext`
188			`verilogSourcefragment`
189
190
191
192
193
194
195
196			`fs-sim`
197
198
199
200			`../verilog/common/top.bus32_big_tb`
201			`verilogSourcemodule`
202
203
204
205
206
207
208			`fs-lint`
209
210
211
212			`../verilog/common/top.bus32_big_tb`
213			`verilogSourcemodule`
214
215
216
217
218
219
220
221
222
223
224
225
226

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bus32_big_tb.xml] - Blame information for rev 133