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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bus32_lit_lint.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
wishbone
wb_uart16550
bus32_lit_lint
 

 

  elab_verilog
  102.1
  none
  :*Simulation:*
>
  ./tools/verilog/elab_verilog
    
    
      configuration
      default
    
    
      dest_dir
      io_ports
    
  

 

  gen_design
  102.1
  none
  :*Simulation:*
>
  ./tools/verilog/gen_design
    
    
      dest_dir
      io_ports
    
  

 

 
 
 
 

 
 
 
       
 
 
              
              Dut
              
              
                                   spirit:library="wishbone"
                                   spirit:name="wb_uart16550"
                                   spirit:version="bus32_lit_dut.params"/>
              
              
 
 
              
              lint
              :*Lint:*
              Verilog
              fs-lint
              
 
 
              
              rtl_check
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="rtl_check"/>
              
              
 
      
 
 
 
 

 
 
 
 
  
 
 
 
 
    
      fs-lint
 
      
        
        ../verilog/lint/wb_uart16550_bus32_lit_lint
        verilogSource
        module
      
 
    
 
 
 
 
 
  
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`wishbone`
39			`wb_uart16550`
40			`bus32_lit_lint`
41
42	133	jt_eaton
43	131	jt_eaton
44	133	jt_eaton
45			`elab_verilog`
46			`102.1`
47			`none`
48			`:Simulation:`
49			`>`
50			`./tools/verilog/elab_verilog`
51
52
53			`configuration`
54			`default`
55
56
57			`dest_dir`
58			`io_ports`
59
60
61
62	131	jt_eaton
63	133	jt_eaton
64			`gen_design`
65			`102.1`
66			`none`
67			`:Simulation:`
68			`>`
69			`./tools/verilog/gen_design`
70
71
72			`dest_dir`
73			`io_ports`
74
75
76
77	131	jt_eaton
78	133	jt_eaton
79	131	jt_eaton
80	133	jt_eaton
81
82
83	131	jt_eaton
84
85
86
87
88
89
90
91			`Dut`
92
93
94			`spirit:library="wishbone"`
95			`spirit:name="wb_uart16550"`
96			`spirit:version="bus32_lit_dut.params"/>`
97
98
99
100
101
102			`lint`
103			`:Lint:`
104			`Verilog`
105			`fs-lint`
106
107
108
109
110			`rtl_check`
111
112
113			`spirit:library="Testbench"`
114			`spirit:name="toolflow"`
115			`spirit:version="rtl_check"/>`
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135			`fs-lint`
136
137
138
139			`../verilog/lint/wb_uart16550_bus32_lit_lint`
140			`verilogSource`
141			`module`
142
143
144
145
146
147
148
149
150
151
152
153
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156

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bus32_lit_lint.xml] - Blame information for rev 133