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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_def_tb.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
wishbone
wb_uart16550
def_tb
 
 
 
 
 
 
 

 

  elab_verilog
  103.0
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog

 

  trace_bus
  103.0
  none
  :*Simulation:*
  ./tools/verilog/trace_bus
    
    
      path
      root.dut
    
    
      bus_name
      wb
    
  
 

 
 
 

  gen_header
  102.0
  none
  headers
  ./tools/regtool/gen_header
    
    
      inst_path
      dut.wb
    
    
      dest_dir
      ../../../sw/
    
  

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top.tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 
 
 
 

 
 

 
 

    UART_MODEL_CLKCNT4'b1100
    UART_MODEL_SIZE4

 
 
 
 
 
       
 
 
              
              Params
              
              
                                   spirit:library="wishbone"
                                   spirit:name="wb_uart16550"
                                   spirit:version="def_dut.params"/>
              
              
 
 
              
              Bfm
              
                                   spirit:library="wishbone"
                                   spirit:name="wb_uart16550"
                                   spirit:version="bfm.design"/>
              
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              headersheaders
              Verilog
              
              
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
 
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 
 
 
 

 
 
 
  
 
 
    
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
    
 
 
 
 
 
    
      fs-sim
 
      
        
        ../verilog/common/top.tb
        verilogSourcemodule
      
 
 
 
    
 
 
    
      fs-lint
 
      
        
        ../verilog/common/top.tb
        verilogSourcemodule
      
 
 
    
 
 
 
 
  
 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_def_tb.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`wishbone`
39			`wb_uart16550`
40			`def_tb`
41
42
43
44
45
46
47
48
49
50
51			`elab_verilog`
52			`103.0`
53			`none`
54			`:Simulation:`
55			`./tools/verilog/elab_verilog`
56
57
58
59			`trace_bus`
60			`103.0`
61			`none`
62			`:Simulation:`
63			`./tools/verilog/trace_bus`
64
65
66			`path`
67			`root.dut`
68
69
70			`bus_name`
71			`wb`
72
73
74
75
76
77
78
79
80			`gen_header`
81			`102.0`
82			`none`
83			`headers`
84			`./tools/regtool/gen_header`
85
86
87			`inst_path`
88			`dut.wb`
89
90
91			`dest_dir`
92			`../../../sw/`
93
94
95
96
97
98
99
100
101			`gen_verilog`
102			`104.0`
103			`none`
104			`common`
105			`./tools/verilog/gen_verilog`
106
107
108			`destination`
109			`top.tb`
110
111
112			`dest_dir`
113			`../verilog`
114
115
116			`top`
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133			`UART_MODEL_CLKCNT4'b1100`
134			`UART_MODEL_SIZE4`
135
136
137
138
139
140
141
142
143
144
145			`Params`
146
147
148			`spirit:library="wishbone"`
149			`spirit:name="wb_uart16550"`
150			`spirit:version="def_dut.params"/>`
151
152
153
154
155
156			`Bfm`
157
158			`spirit:library="wishbone"`
159			`spirit:name="wb_uart16550"`
160			`spirit:version="bfm.design"/>`
161
162
163
164
165			`icarus`
166
167
168			`spirit:library="Testbench"`
169			`spirit:name="toolflow"`
170			`spirit:version="icarus"/>`
171
172
173
174
175
176
177
178			`headersheaders`
179			`Verilog`
180
181
182
183
184
185
186			`commoncommon`
187			`Verilog`
188
189
190			`fs-common`
191
192
193
194
195
196
197			`sim:Simulation:`
198			`Verilog`
199
200
201			`fs-sim`
202
203
204
205
206			`lint:Lint:`
207			`Verilog`
208
209
210			`fs-lint`
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230			`fs-common`
231
232
233
234			`../verilog/tb.ext`
235			`verilogSourcefragment`
236
237
238
239
240
241
242
243
244
245			`fs-sim`
246
247
248
249			`../verilog/common/top.tb`
250			`verilogSourcemodule`
251
252
253
254
255
256
257
258
259			`fs-lint`
260
261
262
263			`../verilog/common/top.tb`
264			`verilogSourcemodule`
265
266
267
268
269
270
271
272
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