URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_probe/] [rtl/] [xml/] [io_probe_def.xml] - Blame information for rev 131

Go to most recent revision | Details | Compare with Previous | View Log





xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
io_probe
def  default
 
 
 
 
 
 
 

 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.out.sim
    
    
      dest_dir
      ../verilog
    
  

 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.out.syn
    
    
      dest_dir
      ../verilog
    
  

 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 

 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/sim/top.out.sim
        verilogSourcemodule
      
 
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/syn/top.out.syn
        verilogSourcemodule
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
 
 
    
 
 
 
 
 
  
 
 
 
 
 
 
 
 

       
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 

MESG" "
WIDTH1
RESET{WIDTH{1'bz}}
IN_DELAY5
OUT_DELAY15
OUT_WIDTH10

 

 
clk
wire
in

 
 
drive_value
wire
in
WIDTH-10

 
 
expected_value
wire
in
WIDTH-10

 
mask
wire
in
WIDTH-10

 
 
signal
wire
inout
WIDTH-10

 
 
 
 

 

 
 
 
 
 
 
 
 
 


Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_probe/] [rtl/] [xml/] [io_probe_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`io_probe`
40			`def default`
41
42
43
44
45
46
47
48
49
50
51			`gen_verilog_sim`
52			`104.0`
53			`none`
54			`:Simulation:`
55			`./tools/verilog/gen_verilog`
56
57
58			`destination`
59			`top.out.sim`
60
61
62			`dest_dir`
63			`../verilog`
64
65
66
67
68
69
70			`gen_verilog_syn`
71			`104.0`
72			`none`
73			`:Synthesis:`
74			`./tools/verilog/gen_verilog`
75
76
77			`destination`
78			`top.out.syn`
79
80
81			`dest_dir`
82			`../verilog`
83
84
85
86
87
88
89
90			`gen_verilogLib_sim`
91			`105.0`
92			`none`
93			`:Simulation:`
94			`./tools/verilog/gen_verilogLib`
95
96
97			`dest_dir`
98			`../views`
99
100
101			`view`
102			`sim`
103
104
105
106
107
108
109
110			`gen_verilogLib_syn`
111			`105.0`
112			`none`
113			`:Synthesis:`
114			`./tools/verilog/gen_verilogLib`
115
116
117			`dest_dir`
118			`../views`
119
120
121			`view`
122			`syn`
123
124
125
126
127
128
129
130
131
132
133
134			`fs-sim`
135
136
137
138			`../verilog/copyright.v`
139			`verilogSourceinclude`
140
141
142
143
144			`../verilog/sim/top.out.sim`
145			`verilogSourcemodule`
146
147
148
149
150
151			`../verilog/top.body`
152			`verilogSourcefragment`
153
154
155
156			`dest_dir../views/sim/`
157			`verilogSourcelibraryDir`
158
159
160
161
162
163
164
165
166
167
168			`fs-syn`
169
170
171
172			`../verilog/copyright.v`
173			`verilogSourceinclude`
174
175
176
177
178			`../verilog/syn/top.out.syn`
179			`verilogSourcemodule`
180
181
182
183			`dest_dir../views/syn/`
184			`verilogSourcelibraryDir`
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211			`sim:Simulation:`
212
213			`Verilog`
214
215
216			`fs-sim`
217
218
219
220
221			`syn:Synthesis:`
222
223			`Verilog`
224
225
226			`fs-syn`
227
228
229
230
231
232			`doc`
233
234
235			`spirit:library="Testbench"`
236			`spirit:name="toolflow"`
237			`spirit:version="documentation"/>`
238
239			`:Documentation:`
240			`Verilog`
241
242
243
244
245
246
247
248			`MESG" "`
249			`WIDTH1`
250			`RESET{WIDTH{1'bz}}`
251			`IN_DELAY5`
252			`OUT_DELAY15`
253			`OUT_WIDTH10`
254
255
256
257
258			`clk`
259			`wire`
260			`in`
261
262
263
264			`drive_value`
265			`wire`
266			`in`
267			`WIDTH-10`
268
269
270
271			`expected_value`
272			`wire`
273			`in`
274			`WIDTH-10`
275
276
277			`mask`
278			`wire`
279			`in`
280			`WIDTH-10`
281
282
283
284			`signal`
285			`wire`
286			`inout`
287			`WIDTH-10`
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305