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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_probe/] [rtl/] [xml/] [io_probe_in.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
io_probe
in  default
 
 
 
 
 
 
 

 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.out.sim
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.out.syn
    
    
      dest_dir
      ../verilog
    
  

 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 

 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/sim/top.out.sim
        verilogSourcemodule
      
 
 
      
        
        ../verilog/top.body.in
        verilogSourcefragment
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/syn/top.out.syn
        verilogSourcemodule
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
 
 
    
 
 
 
 
 
  
 
 
 
 
 
 
 
 

       
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 

MESG" "
WIDTH1
IN_DELAY5

 

 
clk
wire
in

 
 
expected_value
wire
in
WIDTH-10

 
mask
wire
in
WIDTH-10

 
 
signal
wire
in
WIDTH-10

 
 
 
 

 

 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_probe/] [rtl/] [xml/] [io_probe_in.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`io_probe`
40			`in default`
41
42
43
44
45
46
47
48
49
50
51			`gen_verilog_sim`
52			`104.0`
53			`none`
54			`:Simulation:`
55			`./tools/verilog/gen_verilog`
56
57
58			`destination`
59			`top.out.sim`
60
61
62			`dest_dir`
63			`../verilog`
64
65
66
67
68
69			`gen_verilog_syn`
70			`104.0`
71			`none`
72			`:Synthesis:`
73			`./tools/verilog/gen_verilog`
74
75
76			`destination`
77			`top.out.syn`
78
79
80			`dest_dir`
81			`../verilog`
82
83
84
85
86
87
88			`gen_verilogLib_sim`
89			`105.0`
90			`none`
91			`:Simulation:`
92			`./tools/verilog/gen_verilogLib`
93
94
95			`dest_dir`
96			`../views`
97
98
99			`view`
100			`sim`
101
102
103
104
105
106
107			`gen_verilogLib_syn`
108			`105.0`
109			`none`
110			`:Synthesis:`
111			`./tools/verilog/gen_verilogLib`
112
113
114			`dest_dir`
115			`../views`
116
117
118			`view`
119			`syn`
120
121
122
123
124
125
126
127
128
129
130
131			`fs-sim`
132
133
134
135			`../verilog/copyright.v`
136			`verilogSourceinclude`
137
138
139
140
141			`../verilog/sim/top.out.sim`
142			`verilogSourcemodule`
143
144
145
146
147
148			`../verilog/top.body.in`
149			`verilogSourcefragment`
150
151
152
153			`dest_dir../views/sim/`
154			`verilogSourcelibraryDir`
155
156
157
158
159
160
161
162
163
164
165			`fs-syn`
166
167
168
169			`../verilog/copyright.v`
170			`verilogSourceinclude`
171
172
173
174
175			`../verilog/syn/top.out.syn`
176			`verilogSourcemodule`
177
178
179
180			`dest_dir../views/syn/`
181			`verilogSourcelibraryDir`
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208			`sim:Simulation:`
209
210			`Verilog`
211
212
213			`fs-sim`
214
215
216
217
218			`syn:Synthesis:`
219
220			`Verilog`
221
222
223			`fs-syn`
224
225
226
227
228
229			`doc`
230
231
232			`spirit:library="Testbench"`
233			`spirit:name="toolflow"`
234			`spirit:version="documentation"/>`
235
236			`:Documentation:`
237			`Verilog`
238
239
240
241
242
243
244
245			`MESG" "`
246			`WIDTH1`
247			`IN_DELAY5`
248
249
250
251
252			`clk`
253			`wire`
254			`in`
255
256
257
258			`expected_value`
259			`wire`
260			`in`
261			`WIDTH-10`
262
263
264			`mask`
265			`wire`
266			`in`
267			`WIDTH-10`
268
269
270
271			`signal`
272			`wire`
273			`in`
274			`WIDTH-10`
275
276
277
278
279
280
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284
285
286
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