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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_probe/] [rtl/] [xml/] [io_probe_in.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
io_probe
in  default
 
 
 
 
 
 
 

 
 
 

  elab_verilog
  103.0
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.in.sim
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.in.syn
    
    
      dest_dir
      ../verilog
    
  

 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 

 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/sim/top.in.sim
        verilogSourcemodule
      
 
 
      
        
        ../verilog/top.body.in
        verilogSourcefragment
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/syn/top.in.syn
        verilogSourcemodule
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
 
 
    
 
 
 
 
 
  
 
 
 
 
 
 
 
 

       
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 

MESG" "
WIDTH1
IN_DELAY5

 

 
clk
wire
in

 
 
expected_value
wire
in
WIDTH-10

 
mask
wire
in
WIDTH-10

 
 
signal
wire
in
WIDTH-10

 
 
 
 

 

 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_probe/] [rtl/] [xml/] [io_probe_in.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`io_probe`
40			`in default`
41
42
43
44
45
46
47
48
49
50	133	jt_eaton
51
52	131	jt_eaton
53	133	jt_eaton	`elab_verilog`
54			`103.0`
55			`none`
56			`:Simulation:`
57			`./tools/verilog/elab_verilog`
58
59
60			`dest_dir`
61			`io_ports`
62
63
64
65
66
67
68
69
70
71	131	jt_eaton	`gen_verilog_sim`
72			`104.0`
73			`none`
74			`:Simulation:`
75			`./tools/verilog/gen_verilog`
76
77
78			`destination`
79	133	jt_eaton	`top.in.sim`
80	131	jt_eaton
81
82			`dest_dir`
83			`../verilog`
84
85
86
87
88
89			`gen_verilog_syn`
90			`104.0`
91			`none`
92			`:Synthesis:`
93			`./tools/verilog/gen_verilog`
94
95
96			`destination`
97	133	jt_eaton	`top.in.syn`
98	131	jt_eaton
99
100			`dest_dir`
101			`../verilog`
102
103
104
105
106
107
108			`gen_verilogLib_sim`
109			`105.0`
110			`none`
111			`:Simulation:`
112			`./tools/verilog/gen_verilogLib`
113
114
115			`dest_dir`
116			`../views`
117
118
119			`view`
120			`sim`
121
122
123
124
125
126
127			`gen_verilogLib_syn`
128			`105.0`
129			`none`
130			`:Synthesis:`
131			`./tools/verilog/gen_verilogLib`
132
133
134			`dest_dir`
135			`../views`
136
137
138			`view`
139			`syn`
140
141
142
143
144
145
146
147
148
149
150
151			`fs-sim`
152
153
154
155			`../verilog/copyright.v`
156			`verilogSourceinclude`
157
158
159
160
161	133	jt_eaton	`../verilog/sim/top.in.sim`
162	131	jt_eaton	`verilogSourcemodule`
163
164
165
166
167
168			`../verilog/top.body.in`
169			`verilogSourcefragment`
170
171
172
173			`dest_dir../views/sim/`
174			`verilogSourcelibraryDir`
175
176
177
178
179
180
181
182
183
184
185			`fs-syn`
186
187
188
189			`../verilog/copyright.v`
190			`verilogSourceinclude`
191
192
193
194
195	133	jt_eaton	`../verilog/syn/top.in.syn`
196	131	jt_eaton	`verilogSourcemodule`
197
198
199
200			`dest_dir../views/syn/`
201			`verilogSourcelibraryDir`
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
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225
226
227
228			`sim:Simulation:`
229
230			`Verilog`
231
232
233			`fs-sim`
234
235
236
237
238			`syn:Synthesis:`
239
240			`Verilog`
241
242
243			`fs-syn`
244
245
246
247
248
249			`doc`
250
251
252			`spirit:library="Testbench"`
253			`spirit:name="toolflow"`
254			`spirit:version="documentation"/>`
255
256			`:Documentation:`
257			`Verilog`
258
259
260
261
262
263
264
265			`MESG" "`
266			`WIDTH1`
267			`IN_DELAY5`
268
269
270
271
272			`clk`
273			`wire`
274			`in`
275
276
277
278			`expected_value`
279			`wire`
280			`in`
281			`WIDTH-10`
282
283
284			`mask`
285			`wire`
286			`in`
287			`WIDTH-10`
288
289
290
291			`signal`
292			`wire`
293			`in`
294			`WIDTH-10`
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
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312