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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [jtag_model/] [rtl/] [xml/] [jtag_model_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
jtag_model
def  default
 
 
 
 
 
 
 

 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 

 
 
 
  
 
 
 
 
    
      fs-sim
 
 
      
        
        ../verilog/jtag_model_def.v
        verilogSourcemodule
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
    
 
 
 
 
 
 
 
    
      fs-syn
 
      
        
        ../verilog/jtag_model_def.v
        verilogSourcemodule
      
 
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
    
 
 
 
 
 
 
 
  
 
 
 

       
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 

DIVCNT4'h1
SIZE4

 

 
clk
wire
in

 
reset
wire
in

 
 
tclk
reg
out

 
trst_n
reg
out

 
tdo
reg
out

 
tms
reg
out

 
tdi
wire
in

 
 

 

 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [jtag_model/] [rtl/] [xml/] [jtag_model_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`jtag_model`
40			`def default`
41
42
43
44
45
46
47
48
49
50
51
52
53			`gen_verilogLib_sim`
54			`105.0`
55			`none`
56			`:Simulation:`
57			`./tools/verilog/gen_verilogLib`
58
59
60			`dest_dir`
61			`../views`
62
63
64			`view`
65			`sim`
66
67
68
69
70
71
72
73			`gen_verilogLib_syn`
74			`105.0`
75			`none`
76			`:Synthesis:`
77			`./tools/verilog/gen_verilogLib`
78
79
80			`dest_dir`
81			`../views`
82
83
84			`view`
85			`syn`
86
87
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91
92
93
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97
98
99
100			`fs-sim`
101
102
103
104
105			`../verilog/jtag_model_def.v`
106			`verilogSourcemodule`
107
108
109
110			`dest_dir../views/sim/`
111			`verilogSourcelibraryDir`
112
113
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115
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122
123
124
125			`fs-syn`
126
127
128
129			`../verilog/jtag_model_def.v`
130			`verilogSourcemodule`
131
132
133
134
135			`dest_dir../views/syn/`
136			`verilogSourcelibraryDir`
137
138
139
140
141
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143
144
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149
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157
158			`sim:Simulation:`
159			`Verilog`
160
161
162			`fs-sim`
163
164
165
166
167
168			`syn:Synthesis:`
169			`Verilog`
170
171
172			`fs-syn`
173
174
175
176
177
178			`doc`
179
180
181			`spirit:library="Testbench"`
182			`spirit:name="toolflow"`
183			`spirit:version="documentation"/>`
184
185			`:Documentation:`
186			`Verilog`
187
188
189
190
191
192
193
194			`DIVCNT4'h1`
195			`SIZE4`
196
197
198
199
200			`clk`
201			`wire`
202			`in`
203
204
205			`reset`
206			`wire`
207			`in`
208
209
210
211			`tclk`
212			`reg`
213			`out`
214
215
216			`trst_n`
217			`reg`
218			`out`
219
220
221			`tdo`
222			`reg`
223			`out`
224
225
226			`tms`
227			`reg`
228			`out`
229
230
231			`tdi`
232			`wire`
233			`in`
234
235
236
237
238
239
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241
242
243
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245