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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [micro_bus16_model/] [rtl/] [xml/] [micro_bus16_model_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
micro_bus16_model
def  default
 
 
 
 
 
 
 

 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 
 

 
 
 
  
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/top.sim
        verilogSourcemodule
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
    
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/top.syn
        verilogSourcemodule
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
  
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="Testbench"
                                   spirit:name="io_probe"
                                   spirit:version="def.design"/>
              
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
      
 
 
 

OUT_DELAY15
OUT_WIDTH10

 

 
clk
wire
in

 
reset
wire
in

 
addr
reg
out
230

 
wdata
reg
out
150

 
rd
reg
out

 
wr
reg
out

 
lb
reg
out

 
 
ub
reg
out

 
rdata
wire
inout
150

 

 

 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [micro_bus16_model/] [rtl/] [xml/] [micro_bus16_model_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`micro_bus16_model`
40			`def default`
41
42
43
44
45
46
47
48
49
50
51			`gen_verilogLib_sim`
52			`105.0`
53			`none`
54			`:Simulation:`
55			`./tools/verilog/gen_verilogLib`
56
57
58			`dest_dir`
59			`../views`
60
61
62			`view`
63			`sim`
64
65
66
67
68
69
70			`gen_verilogLib_syn`
71			`105.0`
72			`none`
73			`:Synthesis:`
74			`./tools/verilog/gen_verilogLib`
75
76
77			`dest_dir`
78			`../views`
79
80
81			`view`
82			`syn`
83
84
85
86
87
88
89
90
91
92
93
94			`fs-sim`
95
96
97
98			`../verilog/copyright.v`
99			`verilogSourceinclude`
100
101
102
103
104
105			`../verilog/top.sim`
106			`verilogSourcemodule`
107
108
109
110			`dest_dir../views/sim/`
111			`verilogSourcelibraryDir`
112
113
114
115
116
117
118
119
120			`fs-syn`
121
122
123
124			`../verilog/copyright.v`
125			`verilogSourceinclude`
126
127
128
129
130
131			`../verilog/top.syn`
132			`verilogSourcemodule`
133
134
135
136			`dest_dir../views/syn/`
137			`verilogSourcelibraryDir`
138
139
140
141
142
143
144
145
146
147
148
149
150
151			`Hierarchical`
152
153
154			`spirit:library="Testbench"`
155			`spirit:name="io_probe"`
156			`spirit:version="def.design"/>`
157
158
159
160
161
162			`sim:Simulation:`
163
164			`Verilog`
165
166
167			`fs-sim`
168
169
170
171
172			`syn:Synthesis:`
173
174			`Verilog`
175
176
177			`fs-syn`
178
179
180
181
182
183			`doc`
184
185
186			`spirit:library="Testbench"`
187			`spirit:name="toolflow"`
188			`spirit:version="documentation"/>`
189
190			`:Documentation:`
191			`Verilog`
192
193
194
195
196
197
198
199
200
201
202			`OUT_DELAY15`
203			`OUT_WIDTH10`
204
205
206
207
208			`clk`
209			`wire`
210			`in`
211
212
213			`reset`
214			`wire`
215			`in`
216
217
218			`addr`
219			`reg`
220			`out`
221			`230`
222
223
224			`wdata`
225			`reg`
226			`out`
227			`150`
228
229
230			`rd`
231			`reg`
232			`out`
233
234
235			`wr`
236			`reg`
237			`out`
238
239
240			`lb`
241			`reg`
242			`out`
243
244
245
246			`ub`
247			`reg`
248			`out`
249
250
251			`rdata`
252			`wire`
253			`inout`
254			`150`
255
256
257
258
259
260
261
262