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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [mt45w8mw12/] [rtl/] [xml/] [mt45w8mw12_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
mt45w8mw12
def  default
 
 
 
 
 
 
 

 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 
 

 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/top.sim
        verilogSourcemodule
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/top.syn
        verilogSourcemodule
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
    
 
 
  
 
 
 
 
 

       
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 

ADDR_BITS23
DQ_BITS16
MEM_BITS16

 

 
clk
wire
in

 
adv_n
wire
in

 
cre
wire
in

 
o_wait
wire
out

 
 
ce_n
wire
in

 
 
oe_n
wire
in

 
we_n
wire
in

 
 
lb_n
wire
in

 
ub_n
wire
in

 
addr
wire
in
ADDR_BITS-10

 
 
dq
wire
inout
DQ_BITS-10

 
 

 

 
 
 
 
 
 
 
 
 
 
 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [mt45w8mw12/] [rtl/] [xml/] [mt45w8mw12_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`mt45w8mw12`
40			`def default`
41
42
43
44
45
46
47
48
49
50
51			`gen_verilogLib_sim`
52			`105.0`
53			`none`
54			`:Simulation:`
55			`./tools/verilog/gen_verilogLib`
56
57
58			`dest_dir`
59			`../views`
60
61
62			`view`
63			`sim`
64
65
66
67
68
69
70			`gen_verilogLib_syn`
71			`105.0`
72			`none`
73			`:Synthesis:`
74			`./tools/verilog/gen_verilogLib`
75
76
77			`dest_dir`
78			`../views`
79
80
81			`view`
82			`syn`
83
84
85
86
87
88
89
90
91
92
93
94			`fs-sim`
95
96
97
98			`../verilog/copyright.v`
99			`verilogSourceinclude`
100
101
102
103
104			`../verilog/top.sim`
105			`verilogSourcemodule`
106
107
108
109			`dest_dir../views/sim/`
110			`verilogSourcelibraryDir`
111
112
113
114
115
116
117
118
119
120			`fs-syn`
121
122
123
124			`../verilog/copyright.v`
125			`verilogSourceinclude`
126
127
128
129
130			`../verilog/top.syn`
131			`verilogSourcemodule`
132
133
134
135			`dest_dir../views/syn/`
136			`verilogSourcelibraryDir`
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154			`sim:Simulation:`
155
156			`Verilog`
157
158
159			`fs-sim`
160
161
162
163
164			`syn:Synthesis:`
165
166			`Verilog`
167
168
169			`fs-syn`
170
171
172
173
174
175			`doc`
176
177
178			`spirit:library="Testbench"`
179			`spirit:name="toolflow"`
180			`spirit:version="documentation"/>`
181
182			`:Documentation:`
183			`Verilog`
184
185
186
187
188
189
190
191			`ADDR_BITS23`
192			`DQ_BITS16`
193			`MEM_BITS16`
194
195
196
197
198			`clk`
199			`wire`
200			`in`
201
202
203			`adv_n`
204			`wire`
205			`in`
206
207
208			`cre`
209			`wire`
210			`in`
211
212
213			`o_wait`
214			`wire`
215			`out`
216
217
218
219			`ce_n`
220			`wire`
221			`in`
222
223
224
225			`oe_n`
226			`wire`
227			`in`
228
229
230			`we_n`
231			`wire`
232			`in`
233
234
235
236			`lb_n`
237			`wire`
238			`in`
239
240
241			`ub_n`
242			`wire`
243			`in`
244
245
246			`addr`
247			`wire`
248			`in`
249			`ADDR_BITS-10`
250
251
252
253			`dq`
254			`wire`
255			`inout`
256			`DQ_BITS-10`
257
258
259
260
261
262
263
264
265
266
267
268
269
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271
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