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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [or1200_dbg_model/] [rtl/] [xml/] [or1200_dbg_model_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
or1200_dbg_model
def  default
 
 
 
 
 
 
 
 debug
  
  
    
 
        
         addr
         
         dbg_adr_i
           310
           reg
         
       
 
 
        
         wdata
         
         dbg_dat_i
           310
           reg
         
       
 
 
        
         rdata
         
         dbg_dat_o
           310
         
       
 
 
        
         lss
         
         dbg_lss_o
           30
         
       
 
 
        
         is
         
         dbg_is_o
           10
         
       
 
 
        
         wp
         
         dbg_wp_o
           100
         
       
 
 
 
 
      
        stall
        dbg_stall_i
           reg
           
      
 
 
      
        ewt
        dbg_ewt_i
           reg
         
      
 
 
      
        bp
        dbg_bp_o
       
      
 
 
      
        stb
        dbg_stb_i
           reg

      
 
 
      
        we
        dbg_we_i
           reg

      
 
 
      
        ack
        dbg_ack_o
      
 
 
    
 
 
 
 
 
 
 
 
 
 
 

 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.out.sim
    
    
      dest_dir
      ../verilog
    
  

 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.out.syn
    
    
      dest_dir
      ../verilog
    
  

 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 
 

 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/sim/top.out.sim
        verilogSourcemodule
      
 
 
      
        
        ../verilog/top.task
        verilogSourcefragment
      
 
 
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/syn/top.out.syn
        verilogSourcemodule
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
  
 
 
 
 

       
 
 
              
              Hierarchical
 
              
                                   spirit:library="Testbench"
                                   spirit:name="io_probe"
                                   spirit:version="in.design"/>
              
 
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 

OUT_WIDTH10

 

 
clk
wire
in

 
reset
wire
in

 
 

 

 
 
 
 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [or1200_dbg_model/] [rtl/] [xml/] [or1200_dbg_model_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`or1200_dbg_model`
40			`def default`
41
42
43
44
45
46
47
48			`debug`
49
50
51
52
53
54			`addr`
55
56			`dbg_adr_i`
57			`310`
58			`reg`
59
60
61
62
63
64			`wdata`
65
66			`dbg_dat_i`
67			`310`
68			`reg`
69
70
71
72
73
74			`rdata`
75
76			`dbg_dat_o`
77			`310`
78
79
80
81
82
83			`lss`
84
85			`dbg_lss_o`
86			`30`
87
88
89
90
91
92			`is`
93
94			`dbg_is_o`
95			`10`
96
97
98
99
100
101			`wp`
102
103			`dbg_wp_o`
104			`100`
105
106
107
108
109
110
111
112			`stall`
113			`dbg_stall_i`
114			`reg`
115
116
117
118
119
120			`ewt`
121			`dbg_ewt_i`
122			`reg`
123
124
125
126
127
128			`bp`
129			`dbg_bp_o`
130
131
132
133
134
135			`stb`
136			`dbg_stb_i`
137			`reg`
138
139
140
141
142
143			`we`
144			`dbg_we_i`
145			`reg`
146
147
148
149
150
151			`ack`
152			`dbg_ack_o`
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172			`gen_verilog_sim`
173			`104.0`
174			`none`
175			`:Simulation:`
176			`./tools/verilog/gen_verilog`
177
178
179			`destination`
180			`top.out.sim`
181
182
183			`dest_dir`
184			`../verilog`
185
186
187
188
189
190
191			`gen_verilog_syn`
192			`104.0`
193			`none`
194			`:Synthesis:`
195			`./tools/verilog/gen_verilog`
196
197
198			`destination`
199			`top.out.syn`
200
201
202			`dest_dir`
203			`../verilog`
204
205
206
207
208
209
210
211			`gen_verilogLib_sim`
212			`105.0`
213			`none`
214			`:Simulation:`
215			`./tools/verilog/gen_verilogLib`
216
217
218			`dest_dir`
219			`../views`
220
221
222			`view`
223			`sim`
224
225
226
227
228
229
230			`gen_verilogLib_syn`
231			`105.0`
232			`none`
233			`:Synthesis:`
234			`./tools/verilog/gen_verilogLib`
235
236
237			`dest_dir`
238			`../views`
239
240
241			`view`
242			`syn`
243
244
245
246
247
248
249
250
251
252
253
254
255			`fs-sim`
256
257
258
259			`../verilog/copyright.v`
260			`verilogSourceinclude`
261
262
263
264
265			`../verilog/sim/top.out.sim`
266			`verilogSourcemodule`
267
268
269
270
271
272			`../verilog/top.task`
273			`verilogSourcefragment`
274
275
276
277
278
279			`dest_dir../views/sim/`
280			`verilogSourcelibraryDir`
281
282
283
284
285
286
287
288
289
290
291			`fs-syn`
292
293
294
295			`../verilog/copyright.v`
296			`verilogSourceinclude`
297
298
299
300
301			`../verilog/syn/top.out.syn`
302			`verilogSourcemodule`
303
304
305
306			`dest_dir../views/syn/`
307			`verilogSourcelibraryDir`
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324			`Hierarchical`
325
326
327			`spirit:library="Testbench"`
328			`spirit:name="io_probe"`
329			`spirit:version="in.design"/>`
330
331
332
333
334
335
336
337			`sim:Simulation:`
338
339			`Verilog`
340
341
342			`fs-sim`
343
344
345
346
347			`syn:Synthesis:`
348
349			`Verilog`
350
351
352			`fs-syn`
353
354
355
356
357
358			`doc`
359
360
361			`spirit:library="Testbench"`
362			`spirit:name="toolflow"`
363			`spirit:version="documentation"/>`
364
365			`:Documentation:`
366			`Verilog`
367
368
369
370
371
372
373
374			`OUT_WIDTH10`
375
376
377
378
379			`clk`
380			`wire`
381			`in`
382
383
384			`reset`
385			`wire`
386			`in`
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
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