OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [ps2_host/] [rtl/] [verilog/] [top.sim] - Blame information for rev 131

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 131 jt_eaton
 
2
/**********************************************************************/
3
/*                                                                    */
4
/*             -------                                                */
5
/*            /   SOC  \                                              */
6
/*           /    GEN   \                                             */
7
/*          /     SIM    \                                            */
8
/*          ==============                                            */
9
/*          |            |                                            */
10
/*          |____________|                                            */
11
/*                                                                    */
12
/*  ps2 host model  for simulations                                   */
13
/*                                                                    */
14
/*                                                                    */
15
/*  Author(s):                                                        */
16
/*      - John Eaton, jt_eaton@opencores.org                          */
17
/*                                                                    */
18
/**********************************************************************/
19
/*                                                                    */
20
/*    Copyright (C) <2010>                     */
21
/*                                                                    */
22
/*  This source file may be used and distributed without              */
23
/*  restriction provided that this copyright statement is not         */
24
/*  removed from the file and that any derivative work contains       */
25
/*  the original copyright notice and the associated disclaimer.      */
26
/*                                                                    */
27
/*  This source file is free software; you can redistribute it        */
28
/*  and/or modify it under the terms of the GNU Lesser General        */
29
/*  Public License as published by the Free Software Foundation;      */
30
/*  either version 2.1 of the License, or (at your option) any        */
31
/*  later version.                                                    */
32
/*                                                                    */
33
/*  This source is distributed in the hope that it will be            */
34
/*  useful, but WITHOUT ANY WARRANTY; without even the implied        */
35
/*  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR           */
36
/*  PURPOSE.  See the GNU Lesser General Public License for more      */
37
/*  details.                                                          */
38
/*                                                                    */
39
/*  You should have received a copy of the GNU Lesser General         */
40
/*  Public License along with this source; if not, download it        */
41
/*  from http://www.opencores.org/lgpl.shtml                          */
42
/*                                                                    */
43
/**********************************************************************/
44
 
45
 
46
 
47
module ps2_host_def
48
 
49
(
50
input  wire         clk,
51
input  wire         reset,
52
input  wire         busy,
53
 
54
inout  wire [7:0]   rx_data,
55
input  wire         rx_read,
56
input  wire         rx_full,
57
input  wire         rx_parity_error,
58
input  wire         rx_parity_rcv,
59
input  wire         rx_parity_cal,
60
input  wire         rx_frame_error,
61
inout  wire         tx_ack_error,
62
 
63
output  reg         rx_clr,
64
output reg [7:0]    tx_data,
65
output reg          tx_write
66
);
67
 
68
 
69
reg                 exp_tx_ack_err;
70
reg                 mask_tx_ack_err;
71
 
72
reg   [7:0]         exp_rcv_byte;
73
reg   [7:0]         mask_rcv_byte;
74
 
75
 
76
task automatic next;
77
  input [31:0] num;
78
  repeat (num)       @ (posedge clk);
79
endtask
80
 
81
 
82
 
83
always@(posedge clk)
84
  if(reset)
85
    begin
86
    tx_data              <= 8'h00;
87
    tx_write             <= 1'b0;
88
    rx_clr               <= 1'b0;
89
    exp_tx_ack_err       <= 1'b0;
90
    mask_tx_ack_err      <= 1'b0;
91
    exp_rcv_byte         <= 8'h00;
92
    mask_rcv_byte        <= 8'h00;
93
 
94
 
95
 
96
 end
97
 
98
 
99
task clear_rx_host;
100
 begin
101
 rx_clr               <= 1'b1;
102
 next(1);
103
 rx_clr               <= 1'b0;
104
 end
105
endtask
106
 
107
 
108
 
109
 
110
task send_byte;
111
  input [7:0] byte_out;
112
   begin
113
   $display("%t %m %2h",$realtime ,byte_out  );
114
   tx_data  <= byte_out;
115
   next(1);
116
   tx_write   <= 1'b1;
117
   next(1);
118
   tx_write   <= 1'b0;
119
   next(1);
120
   while(busy)   next(1);
121
   mask_tx_ack_err <= 1'b1;
122
   next(1);
123
   mask_tx_ack_err <= 1'b0;
124
   end
125
endtask // send_byte
126
 
127
 
128
 
129
 
130
io_probe_def
131
#(  .MESG("ps2_host tx_ack error")
132
 )
133
tx_ack_err_tpb
134
(
135
          .clk             ( clk             ),
136
          .drive_value     ( 1'bz            ),
137
          .expected_value  ( exp_tx_ack_err  ),
138
          .mask            ( mask_tx_ack_err ),
139
          .signal          ( tx_ack_error    )
140
);
141
 
142
 
143
 
144
 
145
 
146
task rcv_byte;
147
  input [7:0] byte_in;
148
   begin
149
   exp_rcv_byte  <= byte_in;
150
 
151
   while(!rx_read)  next(1);
152
   $display("%t           checking    %h",$realtime,byte_in);
153
   mask_rcv_byte <= 8'hff;
154
   next(1);
155
   mask_rcv_byte <= 8'h00;
156
end
157
endtask
158
 
159
 
160
 
161
 
162
io_probe_def
163
#(  .MESG("ps2_host receive error"),
164
    .WIDTH        (8)
165
 )
166
rcv_byte_tpb
167
(
168
          .clk             ( clk           ),
169
          .drive_value     ( {8{1'bz}}     ),
170
          .expected_value  ( exp_rcv_byte  ),
171
          .mask            ( mask_rcv_byte ),
172
          .signal          ( rx_data       )
173
);
174
 
175
 
176
 
177
 
178
endmodule
179
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.