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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [ps2_host/] [rtl/] [verilog/] [top.syn] - Blame information for rev 131

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/**********************************************************************/
/*                                                                    */
/*             -------                                                */
/*            /   SOC  \                                              */
/*           /    GEN   \                                             */
/*          /     SIM    \                                            */
/*          ==============                                            */
/*          |            |                                            */
/*          |____________|                                            */
/*                                                                    */
/*  ps2 host model  for simulations                                   */
/*                                                                    */
/*                                                                    */
/*  Author(s):                                                        */
/*      - John Eaton, jt_eaton@opencores.org                          */
/*                                                                    */
/**********************************************************************/
/*                                                                    */
/*    Copyright (C) <2010>  <Ouabache Design Works>                   */
/*                                                                    */
/*  This source file may be used and distributed without              */
/*  restriction provided that this copyright statement is not         */
/*  removed from the file and that any derivative work contains       */
/*  the original copyright notice and the associated disclaimer.      */
/*                                                                    */
/*  This source file is free software; you can redistribute it        */
/*  and/or modify it under the terms of the GNU Lesser General        */
/*  Public License as published by the Free Software Foundation;      */
/*  either version 2.1 of the License, or (at your option) any        */
/*  later version.                                                    */
/*                                                                    */
/*  This source is distributed in the hope that it will be            */
/*  useful, but WITHOUT ANY WARRANTY; without even the implied        */
/*  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR           */
/*  PURPOSE.  See the GNU Lesser General Public License for more      */
/*  details.                                                          */
/*                                                                    */
/*  You should have received a copy of the GNU Lesser General         */
/*  Public License along with this source; if not, download it        */
/*  from http://www.opencores.org/lgpl.shtml                          */
/*                                                                    */
/**********************************************************************/
 
 
 
module ps2_host_def
 
(
input  wire         clk,
input  wire         reset,
input  wire         busy,
 
inout  wire [7:0]   rx_data,
input  wire         rx_read,
input  wire         rx_full,
input  wire         rx_parity_error,
input  wire         rx_parity_rcv,
input  wire         rx_parity_cal,
input  wire         rx_frame_error,
inout  wire         tx_ack_error,
 
output  reg         rx_clr,
output reg [7:0]    tx_data,
output reg          tx_write
);
 
 
reg                 exp_tx_ack_err;
reg                 mask_tx_ack_err;
 
reg   [7:0]         exp_rcv_byte;
reg   [7:0]         mask_rcv_byte;
 
 
 
 
 
always@(posedge clk)
  if(reset)
    begin
    tx_data              <= 8'h00;
    tx_write             <= 1'b0;
    rx_clr               <= 1'b0;
    exp_tx_ack_err       <= 1'b0;
    mask_tx_ack_err      <= 1'b0;
    exp_rcv_byte         <= 8'h00;
    mask_rcv_byte        <= 8'h00;
 end
 
 
 
 
 
 
 
endmodule
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2			`/**********************************************************************/`
3			`/* */`
4			`/* ------- */`
5			`/* / SOC \ */`
6			`/* / GEN \ */`
7			`/* / SIM \ */`
8			`/* ============== */`
9			`/* \| \| */`
10			`/* \|____________\| */`
11			`/* */`
12			`/* ps2 host model for simulations */`
13			`/* */`
14			`/* */`
15			`/* Author(s): */`
16			`/* - John Eaton, jt_eaton@opencores.org */`
17			`/* */`
18			`/**********************************************************************/`
19			`/* */`
20			`/* Copyright (C) <2010> <Ouabache Design Works> */`
21			`/* */`
22			`/* This source file may be used and distributed without */`
23			`/* restriction provided that this copyright statement is not */`
24			`/* removed from the file and that any derivative work contains */`
25			`/* the original copyright notice and the associated disclaimer. */`
26			`/* */`
27			`/* This source file is free software; you can redistribute it */`
28			`/* and/or modify it under the terms of the GNU Lesser General */`
29			`/* Public License as published by the Free Software Foundation; */`
30			`/* either version 2.1 of the License, or (at your option) any */`
31			`/* later version. */`
32			`/* */`
33			`/* This source is distributed in the hope that it will be */`
34			`/* useful, but WITHOUT ANY WARRANTY; without even the implied */`
35			`/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */`
36			`/* PURPOSE. See the GNU Lesser General Public License for more */`
37			`/* details. */`
38			`/* */`
39			`/* You should have received a copy of the GNU Lesser General */`
40			`/* Public License along with this source; if not, download it */`
41			`/* from http://www.opencores.org/lgpl.shtml */`
42			`/* */`
43			`/**********************************************************************/`
44
45
46
47			`module ps2_host_def`
48
49			`(`
50			`input wire clk,`
51			`input wire reset,`
52			`input wire busy,`
53
54			`inout wire [7:0] rx_data,`
55			`input wire rx_read,`
56			`input wire rx_full,`
57			`input wire rx_parity_error,`
58			`input wire rx_parity_rcv,`
59			`input wire rx_parity_cal,`
60			`input wire rx_frame_error,`
61			`inout wire tx_ack_error,`
62
63			`output reg rx_clr,`
64			`output reg [7:0] tx_data,`
65			`output reg tx_write`
66			`);`
67
68
69			`reg exp_tx_ack_err;`
70			`reg mask_tx_ack_err;`
71
72			`reg [7:0] exp_rcv_byte;`
73			`reg [7:0] mask_rcv_byte;`
74
75
76
77
78
79			`always@(posedge clk)`
80			`if(reset)`
81			`begin`
82			`tx_data <= 8'h00;`
83			`tx_write <= 1'b0;`
84			`rx_clr <= 1'b0;`
85			`exp_tx_ack_err <= 1'b0;`
86			`mask_tx_ack_err <= 1'b0;`
87			`exp_rcv_byte <= 8'h00;`
88			`mask_rcv_byte <= 8'h00;`
89			`end`
90
91
92
93
94
95
96
97			`endmodule`
98

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [ps2_host/] [rtl/] [verilog/] [top.syn] - Blame information for rev 131