Subversion Repositories socgen

xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"

xmlns:socgen="http://opencores.org"

xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"

xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014

http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">

opencores.org

Testbench

ps2_host

def

  gen_verilog_sim

  104.0

  none

  :*Simulation:*

  tools/verilog/gen_verilog

      destination

      ps2_host_def

  gen_verilog_syn

  104.0

  none

  :*Synthesis:*

  tools/verilog/gen_verilog

      destination

      ps2_host_def

                                Hierarchical

              Hierarchical

              Hierarchical

              verilog

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="verilog"/>

              sim:*Simulation:*

              Verilog

                            fs-sim

              syn:*Synthesis:*

              Verilog

                            fs-syn

              doc

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="documentation"/>

              :*Documentation:*

              Verilog

clk

wire

in

reset

wire

in

busy

wire

in

rx_read

wire

in

rx_full

wire

in

rx_parity_error

wire

in

rx_parity_rcv

wire

in

rx_parity_cal

wire

in

tx_ack_error

wire

in

rx_frame_error

wire

in

rx_clr

reg

out

tx_write

reg

out

tx_data

reg

out70

rx_data

wire

in70

      fs-sim

        ../verilog/logic

        verilogSourcefragment

        ../verilog/tasks

        verilogSourcefragment

        ../verilog/copyright

        verilogSourceinclude

        ../verilog/sim/ps2_host_def

        verilogSourcemodule

        dest_dir../views/sim/

        verilogSourcelibraryDir

      fs-syn

        ../verilog/logic

        verilogSourcefragment

        ../verilog/copyright

        verilogSourceinclude

        ../verilog/syn/ps2_host_def

        verilogSourcemodule

        dest_dir../views/syn/

        verilogSourcelibraryDir