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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_host/] [rtl/] [xml/] [uart_host_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
uart_host
def  default
 

 

  gen_verilogLib_sim
  105.0
  none
 :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 

  gen_verilogLib_syn
  105.0
  none
 :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 

 
 
  
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/top.sim
        verilogSourcemodule
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
 
    
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/top.syn
        verilogSourcemodule
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
    
 
 
 
  
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="Testbench"
                                   spirit:name="io_probe"
                                   spirit:version="def.design"/>
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 

 
clk
wire
in

 
reset
wire
in

 
 
parity_enable
reg
out

 
txd_parity
reg
out

 
txd_force_parity
reg
out

 
txd_buffer_empty
wire
in

 
rxd_data_avail
wire
in

 
rxd_stop_error
wire
in

 
rxd_parity_error
wire
in

 
 
 
output  reg [7:0]     txd_data_in,
output  reg           txd_load,
output  reg           txd_break,
output  reg           rxd_parity,
output  reg           rxd_force_parity,
output  reg           rxd_data_avail_stb,
inout  wire [7:0]     rxd_data_out,
 
 

 

 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_host/] [rtl/] [xml/] [uart_host_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`uart_host`
40			`def default`
41
42
43
44
45			`gen_verilogLib_sim`
46			`105.0`
47			`none`
48			`:Simulation:`
49			`./tools/verilog/gen_verilogLib`
50
51
52			`dest_dir`
53			`../views`
54
55
56			`view`
57			`sim`
58
59
60
61
62
63			`gen_verilogLib_syn`
64			`105.0`
65			`none`
66			`:Synthesis:`
67			`./tools/verilog/gen_verilogLib`
68
69
70			`dest_dir`
71			`../views`
72
73
74			`view`
75			`syn`
76
77
78
79
80
81
82
83
84
85
86
87			`fs-sim`
88
89
90
91			`../verilog/copyright.v`
92			`verilogSourceinclude`
93
94
95
96
97			`../verilog/top.sim`
98			`verilogSourcemodule`
99
100
101
102			`dest_dir../views/sim/`
103			`verilogSourcelibraryDir`
104
105
106
107
108
109
110
111
112
113			`fs-syn`
114
115
116
117			`../verilog/copyright.v`
118			`verilogSourceinclude`
119
120
121
122
123			`../verilog/top.syn`
124			`verilogSourcemodule`
125
126
127
128			`dest_dir../views/syn/`
129			`verilogSourcelibraryDir`
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144			`Hierarchical`
145
146
147			`spirit:library="Testbench"`
148			`spirit:name="io_probe"`
149			`spirit:version="def.design"/>`
150
151
152
153			`sim:Simulation:`
154
155			`Verilog`
156
157
158			`fs-sim`
159
160
161
162
163			`syn:Synthesis:`
164
165			`Verilog`
166
167
168			`fs-syn`
169
170
171
172
173
174
175			`doc`
176
177
178			`spirit:library="Testbench"`
179			`spirit:name="toolflow"`
180			`spirit:version="documentation"/>`
181
182			`:Documentation:`
183			`Verilog`
184
185
186
187
188
189
190
191			`clk`
192			`wire`
193			`in`
194
195
196			`reset`
197			`wire`
198			`in`
199
200
201
202			`parity_enable`
203			`reg`
204			`out`
205
206
207			`txd_parity`
208			`reg`
209			`out`
210
211
212			`txd_force_parity`
213			`reg`
214			`out`
215
216
217			`txd_buffer_empty`
218			`wire`
219			`in`
220
221
222			`rxd_data_avail`
223			`wire`
224			`in`
225
226
227			`rxd_stop_error`
228			`wire`
229			`in`
230
231
232			`rxd_parity_error`
233			`wire`
234			`in`
235
236
237
238
239			`output reg [7:0] txd_data_in,`
240			`output reg txd_load,`
241			`output reg txd_break,`
242			`output reg rxd_parity,`
243			`output reg rxd_force_parity,`
244			`output reg rxd_data_avail_stb,`
245			`inout wire [7:0] rxd_data_out,`
246
247
248
249
250
251
252
253
254
255
256
257