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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_model/] [rtl/] [verilog/] [divider] - Blame information for rev 131

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/**********************************************************************/
/*                                                                    */
/*             -------                                                */
/*            /   SOC  \                                              */
/*           /    GEN   \                                             */
/*          /     LIB    \                                            */
/*          ==============                                            */
/*          |            |                                            */
/*          |____________|                                            */
/*                                                                    */
/*  Generic model for a rate divider                                  */
/*                                                                    */
/*  Author(s):                                                        */
/*      - John Eaton, jt_eaton@opencores.org                          */
/*                                                                    */
/**********************************************************************/
/*                                                                    */
/*    Copyright (C) <2010>                     */
/*                                                                    */
/*  This source file may be used and distributed without              */
/*  restriction provided that this copyright statement is not         */
/*  removed from the file and that any derivative work contains       */
/*  the original copyright notice and the associated disclaimer.      */
/*                                                                    */
/*  This source file is free software; you can redistribute it        */
/*  and/or modify it under the terms of the GNU Lesser General        */
/*  Public License as published by the Free Software Foundation;      */
/*  either version 2.1 of the License, or (at your option) any        */
/*  later version.                                                    */
/*                                                                    */
/*  This source is distributed in the hope that it will be            */
/*  useful, but WITHOUT ANY WARRANTY; without even the implied        */
/*  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR           */
/*  PURPOSE.  See the GNU Lesser General Public License for more      */
/*  details.                                                          */
/*                                                                    */
/*  You should have received a copy of the GNU Lesser General         */
/*  Public License along with this source; if not, download it        */
/*  from http://www.opencores.org/lgpl.shtml                          */
/*                                                                    */
/**********************************************************************/
 
 
 
module
uart_model_divider
 
#(parameter   SIZE=4,
  parameter   SAMPLE=0,
  parameter   RESET=1
 )
(
input  wire              clk,
input  wire              reset,
input  wire              enable,
input  wire [SIZE-1:0]   divider_in,
output  reg              divider_out
                         );
 
reg  [SIZE-1:0]        divide_cnt;
 
always@(posedge clk)
  if(reset)            divider_out    <= RESET;
  else
  if(!enable)          divider_out    <= 1'b0;
  else                 divider_out    <=  ( divide_cnt == SAMPLE );
 
 
 
always@(posedge clk)
  if(reset)            divide_cnt    <= divider_in;
  else
  if(!enable)          divide_cnt    <= divide_cnt;
  else
  if(!(|divide_cnt))   divide_cnt    <= divider_in;
  else                 divide_cnt    <= divide_cnt - 'b1;
 
 
 
 
 
 
endmodule
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2			`/**********************************************************************/`
3			`/* */`
4			`/* ------- */`
5			`/* / SOC \ */`
6			`/* / GEN \ */`
7			`/* / LIB \ */`
8			`/* ============== */`
9			`/* \| \| */`
10			`/* \|____________\| */`
11			`/* */`
12			`/* Generic model for a rate divider */`
13			`/* */`
14			`/* Author(s): */`
15			`/* - John Eaton, jt_eaton@opencores.org */`
16			`/* */`
17			`/**********************************************************************/`
18			`/* */`
19			`/* Copyright (C) <2010> */`
20			`/* */`
21			`/* This source file may be used and distributed without */`
22			`/* restriction provided that this copyright statement is not */`
23			`/* removed from the file and that any derivative work contains */`
24			`/* the original copyright notice and the associated disclaimer. */`
25			`/* */`
26			`/* This source file is free software; you can redistribute it */`
27			`/* and/or modify it under the terms of the GNU Lesser General */`
28			`/* Public License as published by the Free Software Foundation; */`
29			`/* either version 2.1 of the License, or (at your option) any */`
30			`/* later version. */`
31			`/* */`
32			`/* This source is distributed in the hope that it will be */`
33			`/* useful, but WITHOUT ANY WARRANTY; without even the implied */`
34			`/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */`
35			`/* PURPOSE. See the GNU Lesser General Public License for more */`
36			`/* details. */`
37			`/* */`
38			`/* You should have received a copy of the GNU Lesser General */`
39			`/* Public License along with this source; if not, download it */`
40			`/* from http://www.opencores.org/lgpl.shtml */`
41			`/* */`
42			`/**********************************************************************/`
43
44
45
46			`module`
47			`uart_model_divider`
48
49			`#(parameter SIZE=4,`
50			`parameter SAMPLE=0,`
51			`parameter RESET=1`
52			`)`
53			`(`
54			`input wire clk,`
55			`input wire reset,`
56			`input wire enable,`
57			`input wire [SIZE-1:0] divider_in,`
58			`output reg divider_out`
59			`);`
60
61			`reg [SIZE-1:0] divide_cnt;`
62
63			`always@(posedge clk)`
64			`if(reset) divider_out <= RESET;`
65			`else`
66			`if(!enable) divider_out <= 1'b0;`
67			`else divider_out <= ( divide_cnt == SAMPLE );`
68
69
70
71			`always@(posedge clk)`
72			`if(reset) divide_cnt <= divider_in;`
73			`else`
74			`if(!enable) divide_cnt <= divide_cnt;`
75			`else`
76			`if(!(\|divide_cnt)) divide_cnt <= divider_in;`
77			`else divide_cnt <= divide_cnt - 'b1;`
78
79
80
81
82
83
84			`endmodule`
85
86
87

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_model/] [rtl/] [verilog/] [divider] - Blame information for rev 131