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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_model/] [rtl/] [xml/] [uart_model_def.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
uart_model
def  default
 
 
 
 
 
 
 


  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.out.sim
    
    
      dest_dir
      ../verilog
    
  

 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.out.syn
    
    
      dest_dir
      ../verilog
    
  

 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 

 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/sim/top.out.sim
        verilogSourcemodule
      
 
 
      
        
        ../verilog/top.rtl
        verilogSourcefragment
      
 
 
      
        
        ../verilog/top.tasks
        verilogSourcefragment
      
 
 
      
        
        ../verilog/serial_rcvr
        verilogSourcemodule
      
 
      
        
        ../verilog/serial_xmit
        verilogSourcemodule
      
 
 
      
        
        ../verilog/divider
        verilogSourcemodule
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
 
 
    
 
 
 
 
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/syn/top.out.syn
        verilogSourcemodule
      
 
 
      
        
        ../verilog/top.rtl
        verilogSourcefragment
      
 
 
      
        
        ../verilog/serial_rcvr
        verilogSourcemodule
      
 
      
        
        ../verilog/serial_xmit
        verilogSourcemodule
      
 
 
      
        
        ../verilog/divider
        verilogSourcemodule
      
 
 
 
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 
 
 
  
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="Testbench"
                                   spirit:name="uart_model"
                                   spirit:version="def.design"/>
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 

CLKCNT4'h5
SIZE4

 

 
clk
wire
in

 
reset
wire
in

 
 
txd_in
wire
in

 
rxd_out
wire
out

 

 

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_model/] [rtl/] [xml/] [uart_model_def.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`uart_model`
40			`def default`
41
42
43
44
45
46
47
48
49	133	jt_eaton
50			`elab_verilog`
51			`102.1`
52			`none`
53			`:Simulation:`
54			`./tools/verilog/elab_verilog`
55
56
57			`dest_dir`
58			`io_ports`
59
60
61
62	131	jt_eaton
63	133	jt_eaton
64
65
66	131	jt_eaton
67			`gen_verilog_sim`
68			`104.0`
69			`none`
70			`:Simulation:`
71			`./tools/verilog/gen_verilog`
72
73
74			`destination`
75			`top.out.sim`
76
77
78			`dest_dir`
79			`../verilog`
80
81
82
83
84
85
86			`gen_verilog_syn`
87			`104.0`
88			`none`
89			`:Synthesis:`
90			`./tools/verilog/gen_verilog`
91
92
93			`destination`
94			`top.out.syn`
95
96
97			`dest_dir`
98			`../verilog`
99
100
101
102
103
104
105
106			`gen_verilogLib_sim`
107			`105.0`
108			`none`
109			`:Simulation:`
110			`./tools/verilog/gen_verilogLib`
111
112
113			`dest_dir`
114			`../views`
115
116
117			`view`
118			`sim`
119
120
121
122
123
124			`gen_verilogLib_syn`
125			`105.0`
126			`none`
127			`:Synthesis:`
128			`./tools/verilog/gen_verilogLib`
129
130
131			`dest_dir`
132			`../views`
133
134
135			`view`
136			`syn`
137
138
139
140
141
142
143
144
145
146
147
148			`fs-sim`
149
150
151
152			`../verilog/copyright.v`
153			`verilogSourceinclude`
154
155
156
157
158			`../verilog/sim/top.out.sim`
159			`verilogSourcemodule`
160
161
162
163
164
165			`../verilog/top.rtl`
166			`verilogSourcefragment`
167
168
169
170
171
172			`../verilog/top.tasks`
173			`verilogSourcefragment`
174
175
176
177
178
179			`../verilog/serial_rcvr`
180			`verilogSourcemodule`
181
182
183
184
185			`../verilog/serial_xmit`
186			`verilogSourcemodule`
187
188
189
190
191
192			`../verilog/divider`
193			`verilogSourcemodule`
194
195
196
197			`dest_dir../views/sim/`
198			`verilogSourcelibraryDir`
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215			`fs-syn`
216
217
218
219			`../verilog/copyright.v`
220			`verilogSourceinclude`
221
222
223
224
225			`../verilog/syn/top.out.syn`
226			`verilogSourcemodule`
227
228
229
230
231
232			`../verilog/top.rtl`
233			`verilogSourcefragment`
234
235
236
237
238
239			`../verilog/serial_rcvr`
240			`verilogSourcemodule`
241
242
243
244
245			`../verilog/serial_xmit`
246			`verilogSourcemodule`
247
248
249
250
251
252			`../verilog/divider`
253			`verilogSourcemodule`
254
255
256
257
258
259
260			`dest_dir../views/syn/`
261			`verilogSourcelibraryDir`
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280			`Hierarchical`
281
282
283			`spirit:library="Testbench"`
284	133	jt_eaton	`spirit:name="uart_model"`
285	131	jt_eaton	`spirit:version="def.design"/>`
286
287
288
289			`sim:Simulation:`
290
291			`Verilog`
292
293
294			`fs-sim`
295
296
297
298
299
300			`syn:Synthesis:`
301
302			`Verilog`
303
304
305			`fs-syn`
306
307
308
309
310
311			`doc`
312
313
314			`spirit:library="Testbench"`
315			`spirit:name="toolflow"`
316			`spirit:version="documentation"/>`
317
318			`:Documentation:`
319			`Verilog`
320
321
322
323
324
325
326
327			`CLKCNT4'h5`
328			`SIZE4`
329
330
331
332
333			`clk`
334			`wire`
335			`in`
336
337
338			`reset`
339			`wire`
340			`in`
341
342
343
344			`txd_in`
345			`wire`
346			`in`
347
348
349			`rxd_out`
350			`wire`
351			`out`
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373