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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [vga_model/] [rtl/] [verilog/] [top.rtl] - Blame information for rev 131

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reg [23:0] red_h_cnt;
reg [23:0] green_h_cnt;
reg [23:0] blue_h_cnt;
 
 
reg [23:0] red_h_lat;
reg [23:0] green_h_lat;
reg [23:0] blue_h_lat;
 
 
reg [47:0] v_cnt;
reg [47:0] v_lat;
 
reg hsync;
reg vsync;
 
 
 
always@(posedge clk)
if(reset)             hsync <= 1'b0;
else                  hsync <= !hsync_n;
 
 
always@(posedge clk)
if(reset)             vsync <= 1'b0;
else                  vsync <= !vsync_n;
 
 
 
 
always@(posedge clk)
if(reset || (hsync))               red_h_cnt <= 24'h0;
else                               red_h_cnt <= red_h_cnt + red;
 
always@(posedge clk)
if   (reset)                       red_h_lat <= 24'h0;
else if(!hsync_n &&(!hsync))       red_h_lat <= red_h_cnt;
else                               red_h_lat <= red_h_lat;
 
always@(posedge clk)
if(reset || (hsync))               green_h_cnt <= 24'h0;
else                               green_h_cnt <= green_h_cnt + green;
 
always@(posedge clk)
if   (reset)                       green_h_lat <= 24'h0;
else if(!hsync_n &&(!hsync))       green_h_lat <= green_h_cnt;
else                               green_h_lat <= green_h_lat;
 
always@(posedge clk)
if(reset || (hsync))               blue_h_cnt <= 24'h0;
else                               blue_h_cnt <= blue_h_cnt + blue;
 
always@(posedge clk)
if   (reset)                       blue_h_lat <= 24'h0;
else if(!hsync_n &&(!hsync))       blue_h_lat <= blue_h_lat;
else                               blue_h_lat <= blue_h_cnt;
 
 
 
always@(posedge clk)
if   (reset)                       v_cnt      <= 48'h0;
else if(!hsync_n &&(!hsync))       v_cnt      <= red_h_cnt + green_h_cnt + blue_h_cnt + v_cnt;
else                               v_cnt      <= v_cnt;
 
 
 
 
 
always@(posedge clk)
if   (reset)                       v_lat <= 48'h0;
else if(!vsync_n &&(vsync))        v_lat <= v_cnt;
else                               v_lat <= v_lat;
 
 
 
 
 
 
 
 
/*
io_probe_def
#(.MESG   ("vga data receive error"),
  .WIDTH  (8)
  )
rx_shift_buffer_prb
(
  .clk           ( clk ),
  .drive_value   (8'bzzzzzzzz),
  .expected_value( exp_rx_shift_buffer),
  .mask          ( mask_rx_shift_buffer),
  .signal        ( prb_rx_shift_buffer)
);
 
 
io_probe_def
#(.MESG   ("vga parity error"))
rx_parity_err_prb
(
  .clk           ( clk ),
  .drive_value   (1'bz),
  .expected_value( exp_rx_parity_err),
  .mask          ( mask_rx_parity_err),
  .signal        ( prb_rx_parity_err)
);
 
*/
 
 
 
 
 
 
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
3
4
5
6			`reg [23:0] red_h_cnt;`
7			`reg [23:0] green_h_cnt;`
8			`reg [23:0] blue_h_cnt;`
9
10
11			`reg [23:0] red_h_lat;`
12			`reg [23:0] green_h_lat;`
13			`reg [23:0] blue_h_lat;`
14
15
16			`reg [47:0] v_cnt;`
17			`reg [47:0] v_lat;`
18
19			`reg hsync;`
20			`reg vsync;`
21
22
23
24			`always@(posedge clk)`
25			`if(reset) hsync <= 1'b0;`
26			`else hsync <= !hsync_n;`
27
28
29			`always@(posedge clk)`
30			`if(reset) vsync <= 1'b0;`
31			`else vsync <= !vsync_n;`
32
33
34
35
36			`always@(posedge clk)`
37			`if(reset \|\| (hsync)) red_h_cnt <= 24'h0;`
38			`else red_h_cnt <= red_h_cnt + red;`
39
40			`always@(posedge clk)`
41			`if (reset) red_h_lat <= 24'h0;`
42			`else if(!hsync_n &&(!hsync)) red_h_lat <= red_h_cnt;`
43			`else red_h_lat <= red_h_lat;`
44
45			`always@(posedge clk)`
46			`if(reset \|\| (hsync)) green_h_cnt <= 24'h0;`
47			`else green_h_cnt <= green_h_cnt + green;`
48
49			`always@(posedge clk)`
50			`if (reset) green_h_lat <= 24'h0;`
51			`else if(!hsync_n &&(!hsync)) green_h_lat <= green_h_cnt;`
52			`else green_h_lat <= green_h_lat;`
53
54			`always@(posedge clk)`
55			`if(reset \|\| (hsync)) blue_h_cnt <= 24'h0;`
56			`else blue_h_cnt <= blue_h_cnt + blue;`
57
58			`always@(posedge clk)`
59			`if (reset) blue_h_lat <= 24'h0;`
60			`else if(!hsync_n &&(!hsync)) blue_h_lat <= blue_h_lat;`
61			`else blue_h_lat <= blue_h_cnt;`
62
63
64
65			`always@(posedge clk)`
66			`if (reset) v_cnt <= 48'h0;`
67			`else if(!hsync_n &&(!hsync)) v_cnt <= red_h_cnt + green_h_cnt + blue_h_cnt + v_cnt;`
68			`else v_cnt <= v_cnt;`
69
70
71
72
73
74			`always@(posedge clk)`
75			`if (reset) v_lat <= 48'h0;`
76			`else if(!vsync_n &&(vsync)) v_lat <= v_cnt;`
77			`else v_lat <= v_lat;`
78
79
80
81
82
83
84
85
86			`/*`
87			`io_probe_def`
88			`#(.MESG ("vga data receive error"),`
89			`.WIDTH (8)`
90			`)`
91			`rx_shift_buffer_prb`
92			`(`
93			`.clk ( clk ),`
94			`.drive_value (8'bzzzzzzzz),`
95			`.expected_value( exp_rx_shift_buffer),`
96			`.mask ( mask_rx_shift_buffer),`
97			`.signal ( prb_rx_shift_buffer)`
98			`);`
99
100
101			`io_probe_def`
102			`#(.MESG ("vga parity error"))`
103			`rx_parity_err_prb`
104			`(`
105			`.clk ( clk ),`
106			`.drive_value (1'bz),`
107			`.expected_value( exp_rx_parity_err),`
108			`.mask ( mask_rx_parity_err),`
109			`.signal ( prb_rx_parity_err)`
110			`);`
111
112			`*/`
113
114
115
116
117
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123

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [vga_model/] [rtl/] [verilog/] [top.rtl] - Blame information for rev 131