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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [vga_model/] [rtl/] [xml/] [vga_model_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
vga_model
def  default
 
 
 
 
 
 
 

 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.out.sim
    
    
      dest_dir
      ../verilog
    
  

 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.out.syn
    
    
      dest_dir
      ../verilog
    
  

 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 

 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/sim/top.out.sim
        verilogSourcemodule
      
 
 
      
        
        ../verilog/top.rtl
        verilogSourcefragment
      
 
 
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
 
 
    
 
 
 
 
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/syn/top.out.syn
        verilogSourcemodule
      
 
 
      
        
        ../verilog/top.rtl
        verilogSourcefragment
      
 
 
 
 
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 
 
 
  
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="Testbench"
                                   spirit:name="io_probe"
                                   spirit:version="def.design"/>
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 
 
 

 
clk
wire
in

 
reset
wire
in

 
 
vsync_n
wire
in

 
hsync_n
wire
in

 
 
red
wire
in20

 
 
green
wire
in20

 
 
blue
wire
in10

 
 
 
 
 
 

 

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [vga_model/] [rtl/] [xml/] [vga_model_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`vga_model`
40			`def default`
41
42
43
44
45
46
47
48
49
50
51			`gen_verilog_sim`
52			`104.0`
53			`none`
54			`:Simulation:`
55			`./tools/verilog/gen_verilog`
56
57
58			`destination`
59			`top.out.sim`
60
61
62			`dest_dir`
63			`../verilog`
64
65
66
67
68
69
70			`gen_verilog_syn`
71			`104.0`
72			`none`
73			`:Synthesis:`
74			`./tools/verilog/gen_verilog`
75
76
77			`destination`
78			`top.out.syn`
79
80
81			`dest_dir`
82			`../verilog`
83
84
85
86
87
88
89
90			`gen_verilogLib_sim`
91			`105.0`
92			`none`
93			`:Simulation:`
94			`./tools/verilog/gen_verilogLib`
95
96
97			`dest_dir`
98			`../views`
99
100
101			`view`
102			`sim`
103
104
105
106
107
108			`gen_verilogLib_syn`
109			`105.0`
110			`none`
111			`:Synthesis:`
112			`./tools/verilog/gen_verilogLib`
113
114
115			`dest_dir`
116			`../views`
117
118
119			`view`
120			`syn`
121
122
123
124
125
126
127
128
129
130
131
132			`fs-sim`
133
134
135
136			`../verilog/copyright.v`
137			`verilogSourceinclude`
138
139
140
141
142			`../verilog/sim/top.out.sim`
143			`verilogSourcemodule`
144
145
146
147
148
149			`../verilog/top.rtl`
150			`verilogSourcefragment`
151
152
153
154
155
156			`dest_dir../views/sim/`
157			`verilogSourcelibraryDir`
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174			`fs-syn`
175
176
177
178			`../verilog/copyright.v`
179			`verilogSourceinclude`
180
181
182
183
184			`../verilog/syn/top.out.syn`
185			`verilogSourcemodule`
186
187
188
189
190
191			`../verilog/top.rtl`
192			`verilogSourcefragment`
193
194
195
196
197
198
199
200			`dest_dir../views/syn/`
201			`verilogSourcelibraryDir`
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220			`Hierarchical`
221
222
223			`spirit:library="Testbench"`
224			`spirit:name="io_probe"`
225			`spirit:version="def.design"/>`
226
227
228
229			`sim:Simulation:`
230
231			`Verilog`
232
233
234			`fs-sim`
235
236
237
238
239
240			`syn:Synthesis:`
241
242			`Verilog`
243
244
245			`fs-syn`
246
247
248
249
250
251			`doc`
252
253
254			`spirit:library="Testbench"`
255			`spirit:name="toolflow"`
256			`spirit:version="documentation"/>`
257
258			`:Documentation:`
259			`Verilog`
260
261
262
263
264
265
266
267
268
269
270			`clk`
271			`wire`
272			`in`
273
274
275			`reset`
276			`wire`
277			`in`
278
279
280
281			`vsync_n`
282			`wire`
283			`in`
284
285
286			`hsync_n`
287			`wire`
288			`in`
289
290
291
292			`red`
293			`wire`
294			`in20`
295
296
297
298			`green`
299			`wire`
300			`in20`
301
302
303
304			`blue`
305			`wire`
306			`in10`
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
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