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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [doc/] [sch/] [io_host_model_def.sch] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton
v 20100214 1
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C 2400 300 1 0 0 in_port_vector.sym
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{
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T 2400 300 5 10 1 1 0 6 1 1
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refdes=io_host_out_bits[15:0]
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}
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C 2400 700 1 0 0 in_port.sym
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{
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T 2400 700 5 10 1 1 0 6 1 1
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refdes=reset
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}
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C 2400 1100 1 0 0 in_port.sym
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{
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T 2400 1100 5 10 1 1 0 6 1 1
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refdes=io_host_out_valid
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}
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C 2400 1500 1 0 0 in_port.sym
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{
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T 2400 1500 5 10 1 1 0 6 1 1
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refdes=io_host_in_ready
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}
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C 2400 1900 1 0 0 in_port.sym
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{
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T 2400 1900 5 10 1 1 0 6 1 1
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refdes=clk
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}
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C 6000 300  1 0  0 out_port_vector.sym
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{
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T 7000 300 5  10 1 1 0 0 1 1
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refdes=io_host_in_bits[15:0]
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}
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C 6000 700  1 0 0 out_port.sym
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{
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T 7000 700 5  10 1 1 0 0 1 1
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refdes=io_host_out_ready
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}
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C 6000 1100  1 0 0 out_port.sym
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{
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T 7000 1100 5  10 1 1 0 0 1 1
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refdes=io_host_in_valid
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}
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C 6000 1500  1 0 0 out_port.sym
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{
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T 7000 1500 5  10 1 1 0 0 1 1
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refdes=io_host_debug_stats_pcr
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}
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C 6000 1900  1 0 0 out_port.sym
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{
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T 7000 1900 5  10 1 1 0 0 1 1
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refdes=io_host_clk_edge
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}
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C 6000 2300  1 0 0 out_port.sym
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{
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T 7000 2300 5  10 1 1 0 0 1 1
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refdes=io_host_clk
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}

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