URL https://opencores.org/ocsvn/socgen/socgen/trunk

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [doc/] [src/] [geda/] [sch/] [clock_gen_def.sch] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton	`v 20100214 1`
2			`T 40 40 8 10 1 1 0 0 1 1`
3			`refdes=U?`
4			`C 1900 300 1 0 0 in_port.sym`
5			`{`
6			`T 1900 300 5 10 1 1 0 6 1 1`
7			`refdes=BAD`
8			`}`
9			`C 1900 700 1 0 0 in_port.sym`
10			`{`
11			`T 1900 700 5 10 1 1 0 6 1 1`
12			`refdes=STOP`
13			`}`
14			`C 1900 1100 1 0 0 in_port.sym`
15			`{`
16			`T 1900 1100 5 10 1 1 0 6 1 1`
17			`refdes=START`
18			`}`
19			`C 1900 1500 1 0 0 in_port_v.sym`
20			`{`
21			`T 1900 1500 5 10 1 1 0 6 1 1`
22			`refdes=clock__master_clk`
23			`}`
24			`C 7100 300 1 0 0 out_port.sym`
25			`{`
26			`T 8100 300 5 10 1 1 0 0 1 1`
27			`refdes=FINISH`
28			`}`
29			`C 7100 700 1 0 0 out_port.sym`
30			`{`
31			`T 8100 700 5 10 1 1 0 0 1 1`
32			`refdes=FAIL`
33			`}`
34			`C 7100 1100 1 0 0 out_port_v.sym`
35			`{`
36			`T 8100 1100 5 10 1 1 0 0 1 1`
37			`refdes=reset__master_reset`
38			`}`