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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [doc/] [src/] [geda/] [sch/] [testbench.sch] - Blame information for rev 131

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Line No. Rev Author Line
1 131 jt_eaton 
v 20121203 2
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C 4400 5900 1 0 0 in_port.sym
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{
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T 4300 6100 5 10 1 1 0 6 1
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refdes=START
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}
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C 4400 7200 1 0 0 in_port_v.sym
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{
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T 4000 7400 5 10 1 1 0 6 1
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refdes=CLK
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}
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C 5300 2800 1 0 1 out_port.sym
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{
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T 4200 3000 5 10 1 1 0 6 1
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refdes=FINISH
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}
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C 5300 4400 1 0 1 out_port.sym
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{
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T 4100 4600 5 10 1 1 0 6 1
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refdes=FAIL
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}
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B 500 1500 13500 8000 3 0 1 0 -1 -1 0 -1 -1 -1 -1 -1
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B 4400 2300 9000 5500 3 0 1 0 -1 -1 0 -1 -1 -1 -1 -1
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T 700 8700 9 20 1 0 0 0 2
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TESTBENCH
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(SIMULATOR SPECIFIC)
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T 4600 7900 9 20 1 0 0 0 1
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TEST_FIXTURE
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B 1600 6800 1700 1000 3 0 1 0 -1 -1 0 -1 -1 -1 -1 -1
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B 1600 5500 1700 1000 3 0 1 0 -1 -1 0 -1 -1 -1 -1 -1
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B 1600 4000 1700 1000 3 0 1 0 -1 -1 0 -1 -1 -1 -1 -1
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B 1600 2400 1700 1000 3 0 1 0 -1 -1 0 -1 -1 -1 -1 -1
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T 1900 7300 9 10 1 0 0 0 1
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Clock source
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T 2000 6000 9 10 1 0 0 0 1
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Reset source
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T 2000 4500 9 10 1 0 0 0 1
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Fail Counter
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T 1900 2800 9 10 1 0 0 0 2
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Terminate
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 and report
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T 1600 3500 9 10 1 0 0 0 1
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TIMEOUT
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T 1700 7900 9 10 1 0 0 0 1
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PERIOD
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T 7800 8000 9 10 1 0 0 0 6
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Parameters
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PERIOD
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TIMEOUT
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DUT Parameters
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BFM Parameters
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L 3300 7300 4400 7300 3 0 1 0 -1 -1
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L 3300 6000 4400 6000 3 0 1 0 -1 -1
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L 3300 4500 4400 4500 3 0 1 0 -1 -1
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L 3300 2900 4400 2900 3 0 1 0 -1 -1
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B 5300 2600 1600 4900 3 0 1 0 -1 -1 0 -1 -1 -1 -1 -1
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T 5400 7300 9 10 1 0 0 0 1
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clockgen_def
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L 6900 7200 7700 7200 3 0 1 0 -1 -1
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L 6900 5800 7700 5800 3 0 1 0 -1 -1
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L 6900 4500 7700 4500 3 0 1 0 -1 -1
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L 6900 3100 7700 3100 3 0 1 0 -1 -1
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T 7500 7300 9 10 1 0 0 0 1
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clk
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T 7400 5900 9 10 1 0 0 0 1
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reset
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T 7400 4600 9 10 1 0 0 0 1
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bad
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T 7400 3200 9 10 1 0 0 0 1
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stop
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B 10000 5000 1200 1100 3 0 1 0 -1 -1 0 -1 -1 -1 -1 -1
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B 8600 4500 900 1900 3 0 1 0 -1 -1 0 -1 -1 -1 -1 -1
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B 9600 3500 1900 900 3 0 1 0 -1 -1 0 -1 -1 -1 -1 -1
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T 10400 5500 9 10 1 0 0 0 1
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DUT
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T 8900 5400 9 10 1 0 0 0 1
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BFM's
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T 10800 4000 9 10 1 0 180 0 1
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BFM's
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B 11600 4500 900 1900 3 0 1 0 -1 -1 0 -1 -1 -1 -1 -1
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T 11800 5500 9 10 1 0 0 0 1
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BFM's
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B 9600 6500 1900 900 3 0 1 0 -1 -1 0 -1 -1 -1 -1 -1
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T 10800 7000 9 10 1 0 180 0 1
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BFM's
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L 10500 6500 10500 6100 3 0 1 0 -1 -1
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L 10100 6500 10100 6100 3 0 1 0 -1 -1
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L 10900 6500 10900 6100 3 0 1 0 -1 -1
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L 10000 5900 9500 5900 3 0 1 0 -1 -1
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L 10000 5600 9500 5600 3 0 1 0 -1 -1
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L 10000 5300 9500 5300 3 0 1 0 -1 -1
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L 10000 5100 9500 5100 3 0 1 0 -1 -1
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L 10200 5000 10200 4400 3 0 1 0 -1 -1
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L 10600 5000 10600 4400 3 0 1 0 -1 -1
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L 11000 5000 11000 4400 3 0 1 0 -1 -1
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L 11200 5300 11600 5300 3 0 1 0 -1 -1
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L 11200 5500 11600 5500 3 0 1 0 -1 -1
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L 11200 5900 11600 5900 3 0 1 0 -1 -1
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B 10100 5100 1000 900 3 0 1 0 -1 -1 0 -1 -1 -1 -1 -1

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