OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [doc/] [sym/] [io_probe_def.sym] - Blame information for rev 135

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 135 jt_eaton
v 20100214 1
2
B 300 0  4600 1100 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
3
T 400 1250   5 10 1 1 0 0 1 1
4
device=io_probe_def
5
T 400 1450 5 10 1 1 0 0 1 1
6
refdes=U?
7
T 400 1600    0 10 0 1 0 0 1 1
8
vendor=opencores.org
9
T 400 1600    0 10 0 1 0 0 1 1
10
library=Testbench
11
T 400 1600    0 10 0 1 0 0 1 1
12
component=io_probe
13
T 400 1600    0 10 0 1 0 0 1 1
14
version=def
15
P 300 200 0 200 10 1 1
16
{
17
T 400 200 5 10 1 1 0 1 1 1
18
pinnumber=mask[WIDTH-1:0]
19
T 400 200 5 10 0 1 0 1 1 1
20
pinseq=1
21
}
22
P 300 400 0 400 10 1 1
23
{
24
T 400 400 5 10 1 1 0 1 1 1
25
pinnumber=expected_value[WIDTH-1:0]
26
T 400 400 5 10 0 1 0 1 1 1
27
pinseq=2
28
}
29
P 300 600 0 600 10 1 1
30
{
31
T 400 600 5 10 1 1 0 1 1 1
32
pinnumber=drive_value[WIDTH-1:0]
33
T 400 600 5 10 0 1 0 1 1 1
34
pinseq=3
35
}
36
P 300 800 0 800 4 0 1
37
{
38
T 400 800 5 10 1 1 0 1 1 1
39
pinnumber=clk
40
T 400 800 5 10 0 1 0 1 1 1
41
pinseq=4
42
}
43
P 4900 200 5200 200 10 1 1
44
{
45
T 4800 200 5  10 1 1 0 7 1 1
46
pinnumber=signal[WIDTH-1:0]
47
T 4800 200 5  10 0 1 0 7 1 1
48
pinseq=5
49
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.