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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [toolflows/] [toolflow/] [xml/] [icarus.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
toolflow
icarus
 

 
 

  gen_filelists
  104.0
  none
  
    :*Simulation:*
    :*Synthesis:*
  
  ./tools/sys/gen_child_filelist
  
    
      top_file
      ./TestBench
    
    
      top
    
  

 
 

  gen_cov_filelist
  104.0
  none
  
    :*Lint:*
  
  ./tools/sys/gen_child_filelist
  
    
      top_file
      "-v ./TestBench"
    
    
      top
    
    
      suffix
      COV
    
    
      leader
      "-v "
    
  

 
 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 
 

  gen_verilogLib_lint
  105.0
  none
  :*Lint:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      lint
    
  

 

 
 
 

 
 
 
 
 
   
      fs-sim
 
      
        dest_dir
        ../views/sim/
        verilogSource
        libraryDir
      
 
   
 
 
 
 
   
      fs-syn
 
      
        dest_dir
        ../views/syn/
        verilogSource
        libraryDir
      
 
   
 
 
 
   
      fs-lint
 
      
        dest_dir
        ../views/lint/
        verilogSource
        libraryDir
      
 
   
 
 
 
 
 
 
 

 
 
 
 
 
 

 
     
        PERIOD40
        TIMEOUT100000
      
 
 
 
       
 
 
              
              Bfm
              
                                   spirit:library="Testbench"
                                   spirit:name="clock_gen"
                                   spirit:version="bfm.design"/>
              
 
 
              
              sim
              :*Simulation:*
              Verilog
              
              fs-sim
              
 
 
              
              syn
              :*Synthesis:*
              Verilog
              
              fs-syn
              
 
 
 
              
              lint
              :*Lint:*
              Verilog
              
              fs-lint
              
 
 
 
 
      
 
 
 
 
 
 
 
 
 
 
 
 
 

 
clk
  wire
  in

 
START
  wire
  in

 
 
FAIL
  wire
  out

 
 
 
FINISH
  wire
  out

 
 

 

 

 
 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [toolflows/] [toolflow/] [xml/] [icarus.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`toolflow`
40			`icarus`
41
42
43
44
45
46			`gen_filelists`
47			`104.0`
48			`none`
49
50			`:Simulation:`
51			`:Synthesis:`
52
53			`./tools/sys/gen_child_filelist`
54
55
56			`top_file`
57			`./TestBench`
58
59
60			`top`
61
62
63
64
65
66
67			`gen_cov_filelist`
68			`104.0`
69			`none`
70
71			`:Lint:`
72
73			`./tools/sys/gen_child_filelist`
74
75
76			`top_file`
77			`"-v ./TestBench"`
78
79
80			`top`
81
82
83			`suffix`
84			`COV`
85
86
87			`leader`
88			`"-v "`
89
90
91
92
93
94
95
96
97			`gen_verilogLib_sim`
98			`105.0`
99			`none`
100			`:Simulation:`
101			`./tools/verilog/gen_verilogLib`
102
103
104			`dest_dir`
105			`../views`
106
107
108			`view`
109			`sim`
110
111
112
113
114
115
116			`gen_verilogLib_syn`
117			`105.0`
118			`none`
119			`:Synthesis:`
120			`./tools/verilog/gen_verilogLib`
121
122
123			`dest_dir`
124			`../views`
125
126
127			`view`
128			`syn`
129
130
131
132
133
134
135			`gen_verilogLib_lint`
136			`105.0`
137			`none`
138			`:Lint:`
139			`./tools/verilog/gen_verilogLib`
140
141
142			`dest_dir`
143			`../views`
144
145
146			`view`
147			`lint`
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163			`fs-sim`
164
165
166			`dest_dir`
167			`../views/sim/`
168			`verilogSource`
169			`libraryDir`
170
171
172
173
174
175
176
177
178			`fs-syn`
179
180
181			`dest_dir`
182			`../views/syn/`
183			`verilogSource`
184			`libraryDir`
185
186
187
188
189
190
191
192			`fs-lint`
193
194
195			`dest_dir`
196			`../views/lint/`
197			`verilogSource`
198			`libraryDir`
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219			`PERIOD40`
220			`TIMEOUT100000`
221
222
223
224
225
226
227
228
229			`Bfm`
230
231			`spirit:library="Testbench"`
232			`spirit:name="clock_gen"`
233			`spirit:version="bfm.design"/>`
234
235
236
237
238			`sim`
239			`:Simulation:`
240			`Verilog`
241
242			`fs-sim`
243
244
245
246
247			`syn`
248			`:Synthesis:`
249			`Verilog`
250
251			`fs-syn`
252
253
254
255
256
257			`lint`
258			`:Lint:`
259			`Verilog`
260
261			`fs-lint`
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283			`clk`
284			`wire`
285			`in`
286
287
288			`START`
289			`wire`
290			`in`
291
292
293
294			`FAIL`
295			`wire`
296			`out`
297
298
299
300
301			`FINISH`
302			`wire`
303			`out`
304
305
306
307
308
309
310
311
312
313
314
315
316
317