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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [verilog/] [sim/] [clock_dll.v] - Blame information for rev 131

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/**********************************************************************/
/*                                                                    */
/*                                                                    */
/*   Copyright (c) 2012 Ouabache Design Works                         */
/*                                                                    */
/*          All Rights Reserved Worldwide                             */
/*                                                                    */
/*   Licensed under the Apache License,Version2.0 (the'License');     */
/*   you may not use this file except in compliance with the License. */
/*   You may obtain a copy of the License at                          */
/*                                                                    */
/*       http://www.apache.org/licenses/LICENSE-2.0                   */
/*                                                                    */
/*   Unless required by applicable law or agreed to in                */
/*   writing, software distributed under the License is               */
/*   distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES              */
/*   OR CONDITIONS OF ANY KIND, either express or implied.            */
/*   See the License for the specific language governing              */
/*   permissions and limitations under the License.                   */
/**********************************************************************/
 
`timescale 1 ns / 10ps
 
module
cde_clock_dll
#(parameter   DIV=4  ,
  parameter   MULT=2 ,
  parameter   SIZE=4
) (
input   wire        ref_clk,         // input clock
input   wire        reset,           // input reset
output  reg         dll_clk_out,     // output clock at higher frequency
output  reg         div_clk_out      // output clock at synthesized frequency
    );
 
 
localparam   MIN_CLK_DELAY = 0.01;
 
 
//****************************************************************************
// Measure the clock in period.  Use the and the multiplication
//   factor to determine the period for the output clock
//****************************************************************************
real  last_edge_time;
real  this_edge_time;   // $realtime when the input clock edges occur
real  ref_clk_period;   // input clock period
real  dll_clk_out_period;   // output clock period
real  clk_delay;
 
 
initial last_edge_time = 0;
initial dll_clk_out_period = 1;
 
always @(posedge ref_clk)
  begin
    this_edge_time   = $realtime;
    ref_clk_period   =  this_edge_time - last_edge_time;
    dll_clk_out_period   = (ref_clk_period) / MULT;
    last_edge_time   =  this_edge_time;
  end
 
 
 
 
 
//*****************************************************************************
//  Create a new clock
//*****************************************************************************
 
 
reg [SIZE-1:0]  divider;
 
 
initial
  begin
    dll_clk_out = 1'b0;
    forever
      begin
        clk_delay = (dll_clk_out_period/2);
        if (clk_delay < MIN_CLK_DELAY)
        clk_delay = MIN_CLK_DELAY;
        #(clk_delay) dll_clk_out = ~dll_clk_out;
      end
  end
 
 
always@(posedge dll_clk_out)
  if ( reset)                 divider   <= DIV/2;
  else if ( divider ==  'b1)  divider   <= DIV/2;
  else                        divider   <= divider - 'b1;
 
always@(posedge dll_clk_out)
  if(reset)  div_clk_out                       <= 1'b0;
  else if   (divider ==  'b1)   div_clk_out    <= !div_clk_out;
  else       div_clk_out                       <= div_clk_out;
 
 
 
endmodule
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton	`/**********************************************************************/`
2			`/* */`
3			`/* */`
4			`/* Copyright (c) 2012 Ouabache Design Works */`
5			`/* */`
6			`/* All Rights Reserved Worldwide */`
7			`/* */`
8			`/* Licensed under the Apache License,Version2.0 (the'License'); */`
9			`/* you may not use this file except in compliance with the License. */`
10			`/* You may obtain a copy of the License at */`
11			`/* */`
12			`/* http://www.apache.org/licenses/LICENSE-2.0 */`
13			`/* */`
14			`/* Unless required by applicable law or agreed to in */`
15			`/* writing, software distributed under the License is */`
16			`/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */`
17			`/* OR CONDITIONS OF ANY KIND, either express or implied. */`
18			`/* See the License for the specific language governing */`
19			`/* permissions and limitations under the License. */`
20			`/**********************************************************************/`
21
22			`timescale 1 ns / 10ps
23
24			`module`
25			`cde_clock_dll`
26			`#(parameter DIV=4 ,`
27			`parameter MULT=2 ,`
28			`parameter SIZE=4`
29			`) (`
30			`input wire ref_clk, // input clock`
31			`input wire reset, // input reset`
32			`output reg dll_clk_out, // output clock at higher frequency`
33			`output reg div_clk_out // output clock at synthesized frequency`
34			`);`
35
36
37			`localparam MIN_CLK_DELAY = 0.01;`
38
39
40			`//****************************************************************************`
41			`// Measure the clock in period. Use the and the multiplication`
42			`// factor to determine the period for the output clock`
43			`//****************************************************************************`
44			`real last_edge_time;`
45			`real this_edge_time; // $realtime when the input clock edges occur`
46			`real ref_clk_period; // input clock period`
47			`real dll_clk_out_period; // output clock period`
48			`real clk_delay;`
49
50
51			`initial last_edge_time = 0;`
52			`initial dll_clk_out_period = 1;`
53
54			`always @(posedge ref_clk)`
55			`begin`
56			`this_edge_time = $realtime;`
57			`ref_clk_period = this_edge_time - last_edge_time;`
58			`dll_clk_out_period = (ref_clk_period) / MULT;`
59			`last_edge_time = this_edge_time;`
60			`end`
61
62
63
64
65
66			`//*****************************************************************************`
67			`// Create a new clock`
68			`//*****************************************************************************`
69
70
71			`reg [SIZE-1:0] divider;`
72
73
74			`initial`
75			`begin`
76			`dll_clk_out = 1'b0;`
77			`forever`
78			`begin`
79			`clk_delay = (dll_clk_out_period/2);`
80			`if (clk_delay < MIN_CLK_DELAY)`
81			`clk_delay = MIN_CLK_DELAY;`
82			`#(clk_delay) dll_clk_out = ~dll_clk_out;`
83			`end`
84			`end`
85
86
87			`always@(posedge dll_clk_out)`
88			`if ( reset) divider <= DIV/2;`
89			`else if ( divider == 'b1) divider <= DIV/2;`
90			`else divider <= divider - 'b1;`
91
92			`always@(posedge dll_clk_out)`
93			`if(reset) div_clk_out <= 1'b0;`
94			`else if (divider == 'b1) div_clk_out <= !div_clk_out;`
95			`else div_clk_out <= div_clk_out;`
96
97
98
99			`endmodule`
100
101

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [verilog/] [sim/] [clock_dll.v] - Blame information for rev 131