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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [xml/] [cde_clock_gater.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
clock
gater  default
 
 
 
 

 
 
 
 
 

 
 

 
   
      fs-sim
 
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 

 
 
 
 
 
 
 
 

       
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
             
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
 
 
 

 
enable
wire
in

 
clk_in
wire
in

 
atg_clk_mode
wire
in

 
 
 
clk_out
wire
out

 
 
 
 
 

 

 
 
 
 
 
 
 
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
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6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`clock`
15			`gater default`
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32			`fs-sim`
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36			`dest_dir`
37			`../verilog/`
38			`verilogSourcelibraryDir`
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45			`fs-syn`
46
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48			`dest_dir`
49			`../verilog/`
50			`verilogSourcelibraryDir`
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60			`fs-lint`
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62			`dest_dir../verilog/`
63			`verilogSourcelibraryDir`
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86			`sim:Simulation:`
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88			`Verilog`
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91			`fs-sim`
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96			`syn:Synthesis:`
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98			`Verilog`
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101			`fs-syn`
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108			`doc`
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111			`spirit:library="Testbench"`
112			`spirit:name="toolflow"`
113			`spirit:version="documentation"/>`
114
115			`:Documentation:`
116			`Verilog`
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127			`enable`
128			`wire`
129			`in`
130
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132			`clk_in`
133			`wire`
134			`in`
135
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137			`atg_clk_mode`
138			`wire`
139			`in`
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144			`clk_out`
145			`wire`
146			`out`
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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [xml/] [cde_clock_gater.xml] - Blame information for rev 131