OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [xml/] [cde_clock_testmux.xml] - Blame information for rev 131

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 131 jt_eaton
2
5
6
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
7
xmlns:socgen="http://opencores.org"
8
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
9
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
10
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
11
 
12
opencores.org
13
cde
14
clock
15
testmux  default
16
 
17
 
18
 
19
20
 
21
 
22
 
23
 
24
 
25
26
 
27
 
28
 
29
30
 
31
   
32
      fs-sim
33
 
34
 
35
      
36
        dest_dir
37
        ../verilog/
38
        verilogSourcelibraryDir
39
      
40
 
41
  
42
 
43
 
44
   
45
      fs-syn
46
 
47
      
48
        dest_dir
49
        ../verilog/
50
        verilogSourcelibraryDir
51
      
52
 
53
 
54
 
55
   
56
 
57
 
58
    
59
 
60
      fs-lint
61
      
62
        dest_dir
63
        ../verilog/
64
        verilogSourcelibraryDir
65
      
66
 
67
    
68
 
69
 
70
 
71
 
72
 
73
74
 
75
 
76
 
77
 
78
 
79
 
80
 
81
82
       
83
 
84
 
85
              
86
              sim:*Simulation:*
87
              Verilog
88
              
89
                     
90
                            fs-sim
91
                     
92
              
93
 
94
              
95
              syn:*Synthesis:*
96
              Verilog
97
              
98
                     
99
                            fs-syn
100
                     
101
              
102
 
103
 
104
            
105
              doc
106
              
107
              
108
                                   spirit:library="Testbench"
109
                                   spirit:name="toolflow"
110
                                   spirit:version="documentation"/>
111
              
112
              :*Documentation:*
113
              Verilog
114
              
115
 
116
 
117
 
118
 
119
      
120
 
121
 
122
 
123
 
124
125
 
126
sel
127
wire
128
in
129
130
 
131
clk_0
132
wire
133
in
134
135
 
136
clk_1
137
wire
138
in
139
140
 
141
 
142
 
143
clk_out
144
wire
145
out
146
147
 
148
 
149
 
150
 
151
 
152
153
 
154
155
 
156
 
157
 
158
 
159
 
160
 
161
 
162
 
163
 
164
 
165
 
166
 
167
 
168

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.