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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [divider/] [rtl/] [verilog/] [divider_def.v] - Blame information for rev 131

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module
cde_divider_def
 
#(parameter   SIZE=4,
  parameter   SAMPLE=0,
  parameter   RESET=1
 )
(
input  wire              clk,
input  wire              reset,
input  wire              enable,
input  wire [SIZE-1:0]   divider_in,
output  reg              divider_out
                         );
 
reg  [SIZE-1:0]        divide_cnt;
 
always@(posedge clk)
  if(reset)            divider_out    <= RESET;
  else
  if(!enable)          divider_out    <= 1'b0;
  else                 divider_out    <=  ( divide_cnt == SAMPLE );
 
 
 
always@(posedge clk)
  if(reset)            divide_cnt    <= divider_in;
  else
  if(!enable)          divide_cnt    <= divide_cnt;
  else
  if(!(|divide_cnt))   divide_cnt    <= divider_in;
  else                 divide_cnt    <= divide_cnt - 'b1;
 
 
 
 
 
 
endmodule
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton	`module`
2			`cde_divider_def`
3
4			`#(parameter SIZE=4,`
5			`parameter SAMPLE=0,`
6			`parameter RESET=1`
7			`)`
8			`(`
9			`input wire clk,`
10			`input wire reset,`
11			`input wire enable,`
12			`input wire [SIZE-1:0] divider_in,`
13			`output reg divider_out`
14			`);`
15
16			`reg [SIZE-1:0] divide_cnt;`
17
18			`always@(posedge clk)`
19			`if(reset) divider_out <= RESET;`
20			`else`
21			`if(!enable) divider_out <= 1'b0;`
22			`else divider_out <= ( divide_cnt == SAMPLE );`
23
24
25
26			`always@(posedge clk)`
27			`if(reset) divide_cnt <= divider_in;`
28			`else`
29			`if(!enable) divide_cnt <= divide_cnt;`
30			`else`
31			`if(!(\|divide_cnt)) divide_cnt <= divider_in;`
32			`else divide_cnt <= divide_cnt - 'b1;`
33
34
35
36
37
38
39			`endmodule`
40
41
42

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [divider/] [rtl/] [verilog/] [divider_def.v] - Blame information for rev 131