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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [divider/] [rtl/] [xml/] [cde_divider_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
divider
def  default
 
 
 
 

 
 
 
 
 
 

 
 
 

 
   
      fs-sim
 
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
    
 
 
 
 

 
 
 
 
 
 

       
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
          
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 

SIZE4
SAMPLE0
RESET1

 

 
clk
wire
in

 
reset
wire
in

 
 
enable
wire
in

 
 
 
 
divider_in
wire
in
SIZE-10

 
 
divider_out
reg
out

 
 

 

 
 
 
 
 
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`divider`
15			`def default`
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34			`fs-sim`
35
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38			`dest_dir`
39			`../verilog/`
40			`verilogSourcelibraryDir`
41
42
43
44
45
46
47			`fs-syn`
48
49
50			`dest_dir`
51			`../verilog/`
52			`verilogSourcelibraryDir`
53
54
55
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57
58
59
60
61
62			`fs-lint`
63
64			`dest_dir`
65			`../verilog/`
66			`verilogSourcelibraryDir`
67
68
69
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87			`sim:Simulation:`
88			`Verilog`
89
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91			`fs-sim`
92
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96			`syn:Synthesis:`
97			`Verilog`
98
99
100			`fs-syn`
101
102
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105
106			`doc`
107
108
109			`spirit:library="Testbench"`
110			`spirit:name="toolflow"`
111			`spirit:version="documentation"/>`
112
113			`:Documentation:`
114			`Verilog`
115
116
117
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119
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122
123
124			`SIZE4`
125			`SAMPLE0`
126			`RESET1`
127
128
129
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131			`clk`
132			`wire`
133			`in`
134
135
136			`reset`
137			`wire`
138			`in`
139
140
141
142			`enable`
143			`wire`
144			`in`
145
146
147
148
149
150			`divider_in`
151			`wire`
152			`in`
153			`SIZE-10`
154
155
156
157			`divider_out`
158			`reg`
159			`out`
160
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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [divider/] [rtl/] [xml/] [cde_divider_def.xml] - Blame information for rev 131