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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [fifo/] [rtl/] [xml/] [cde_fifo_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
fifo
def  default
 
 
 

 
 
 
 
 
 
 

 
 
 

 
   
      fs-sim
 
 
      
dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
 
 
   
 
    
 
      fs-lint
      
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 

 
 
 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="cde"
                                   spirit:name="fifo"
                                   spirit:version="def.design"/>
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
 
        
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
      
 
 
 

WIDTH8
SIZE2
WORDS4

 
 

 
clk
wire
in

 
reset
wire
in

 
push
wire
in

 
pop
wire
in

 
 
 
 
din
wire
in
WIDTH-10

 
 
dout
reg
out
WIDTH-10

 
 
full
reg
out

 
empty
reg
out

 
over_run
reg
out

 
under_run
reg
out

 
 

 

 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [fifo/] [rtl/] [xml/] [cde_fifo_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`fifo`
15			`def default`
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34			`fs-sim`
35
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38			`dest_dir`
39			`../verilog/`
40			`verilogSourcelibraryDir`
41
42
43
44
45
46
47			`fs-syn`
48
49
50			`dest_dir`
51			`../verilog/`
52			`verilogSourcelibraryDir`
53
54
55
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57
58
59
60
61			`fs-lint`
62
63			`dest_dir../verilog/`
64			`verilogSourcelibraryDir`
65
66
67
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85			`Hierarchical`
86
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88			`spirit:library="cde"`
89			`spirit:name="fifo"`
90			`spirit:version="def.design"/>`
91
92
93
94			`sim:Simulation:`
95
96			`Verilog`
97
98
99			`fs-sim`
100
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104			`syn:Synthesis:`
105
106			`Verilog`
107
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109			`fs-syn`
110
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117			`doc`
118
119
120			`spirit:library="Testbench"`
121			`spirit:name="toolflow"`
122			`spirit:version="documentation"/>`
123
124			`:Documentation:`
125			`Verilog`
126
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137			`WIDTH8`
138			`SIZE2`
139			`WORDS4`
140
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142
143
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145			`clk`
146			`wire`
147			`in`
148
149
150			`reset`
151			`wire`
152			`in`
153
154
155			`push`
156			`wire`
157			`in`
158
159
160			`pop`
161			`wire`
162			`in`
163
164
165
166
167
168			`din`
169			`wire`
170			`in`
171			`WIDTH-10`
172
173
174
175			`dout`
176			`reg`
177			`out`
178			`WIDTH-10`
179
180
181
182			`full`
183			`reg`
184			`out`
185
186
187			`empty`
188			`reg`
189			`out`
190
191
192			`over_run`
193			`reg`
194			`out`
195
196
197			`under_run`
198			`reg`
199			`out`
200
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