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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [busDef/] [xml/] [jtag_rpc_rtl.abstractionDefinition.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
 
opencores.org
cde
jtag
rpc_rtl
 

  
 
 
 
   
      clk
      The clock input coordinates all activities for the internal logic within the jtag bus
      
        
          true
        
        
          CLOCK
          optional
        
        
          ENABLE
          illegal
        
        
          RESET
          illegal
        
        
          optional
          1
          out
        
        
          optional
          1
          in
        
        true
      
    
 
 
 
    
      test_logic_reset
      
        
          CLOCK
          illegal
        
        
          ENABLE
          illegal
        
        
          RESET
          optional
        
        
          optional
          1
          out
        
        
          optional
          1
          in
        
       true
      
    
 
 
    
      run_test
      
        
          CLOCK
          illegal
        
        
          ENABLE
          illegal
        
        
          RESET
          illegal
        
        
          optional
          1
          out
        
        
          optional
          1
          in
        
      
    
 
 
 
    
      select
      
        
          CLOCK
          illegal
        
        
          ENABLE
          illegal
        
        
          RESET
          illegal
        
        
          optional
          1
          out
        
        
          optional
          1
          in
        
      
    
 
 
 
    
      shift_dr
      
        
          CLOCK
          illegal
        
        
          ENABLE
          optional
        
        
          RESET
          illegal
        
        
          optional
          1
          out
        
        
          optional
          1
          in
        
      
    
 
 
 
 
 
    
      capture_dr
      
        
          CLOCK
          illegal
        
        
          ENABLE
          optional
        
        
          RESET
          illegal
        
        
          optional
          1
          out
        
        
          optional
          1
          in
        
      
    
 
 
    
      update_dr
      
        
          CLOCK
          illegal
        
        
          ENABLE
          optional
        
        
          RESET
          illegal
        
        
          optional
          1
          out
        
        
          optional
          1
          in
        
      
    
 
 
 
 
 
 
 
 
    
      tdi
      
        
          CLOCK
          illegal
        
        
          ENABLE
          illegal
        
        
          RESET
          illegal
        
        
          optional
          1
          out
        
        
          optional
          1
          in
        
      
    
 
 
 
 
 
    
      tdo
      
        
          CLOCK
          illegal
        
        
          ENABLE
          illegal
        
        
          RESET
          illegal
        
        
          optional
          1
          in
        
        
          optional
          1
          out
        
      
    
 
 
 
 
 
 
  

 
 
 
 
 
 
 
 
 

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [busDef/] [xml/] [jtag_rpc_rtl.abstractionDefinition.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31	135	jt_eaton
32			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
33	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
34			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
35	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
36			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
37	131	jt_eaton
38
39	135	jt_eaton	`opencores.org`
40			`cde`
41			`jtag`
42			`rpc_rtl`
43	131	jt_eaton
44	135	jt_eaton
45
46	131	jt_eaton
47
48
49	135	jt_eaton
50			`clk`
51			`The clock input coordinates all activities for the internal logic within the jtag bus`
52
53
54			`true`
55
56
57			`CLOCK`
58			`optional`
59
60
61			`ENABLE`
62			`illegal`
63
64
65			`RESET`
66			`illegal`
67
68
69			`optional`
70			`1`
71			`out`
72
73
74			`optional`
75			`1`
76			`in`
77
78			`true`
79
80
81	131	jt_eaton
82
83
84	135	jt_eaton
85			`test_logic_reset`
86
87
88			`CLOCK`
89			`illegal`
90
91
92			`ENABLE`
93			`illegal`
94
95
96			`RESET`
97			`optional`
98
99
100			`optional`
101			`1`
102			`out`
103
104
105			`optional`
106			`1`
107			`in`
108
109			`true`
110
111
112	131	jt_eaton
113
114	135	jt_eaton
115			`run_test`
116
117
118			`CLOCK`
119			`illegal`
120
121
122			`ENABLE`
123			`illegal`
124
125
126			`RESET`
127			`illegal`
128
129
130			`optional`
131			`1`
132			`out`
133
134
135			`optional`
136			`1`
137			`in`
138
139
140
141	131	jt_eaton
142
143
144	135	jt_eaton
145			`select`
146
147
148			`CLOCK`
149			`illegal`
150
151
152			`ENABLE`
153			`illegal`
154
155
156			`RESET`
157			`illegal`
158
159
160			`optional`
161			`1`
162			`out`
163
164
165			`optional`
166			`1`
167			`in`
168
169
170
171	131	jt_eaton
172
173
174	135	jt_eaton
175			`shift_dr`
176
177
178			`CLOCK`
179			`illegal`
180
181
182			`ENABLE`
183			`optional`
184
185
186			`RESET`
187			`illegal`
188
189
190			`optional`
191			`1`
192			`out`
193
194
195			`optional`
196			`1`
197			`in`
198
199
200
201	131	jt_eaton
202
203
204
205
206	135	jt_eaton
207			`capture_dr`
208
209
210			`CLOCK`
211			`illegal`
212
213
214			`ENABLE`
215			`optional`
216
217
218			`RESET`
219			`illegal`
220
221
222			`optional`
223			`1`
224			`out`
225
226
227			`optional`
228			`1`
229			`in`
230
231
232
233	131	jt_eaton
234
235	135	jt_eaton
236			`update_dr`
237
238
239			`CLOCK`
240			`illegal`
241
242
243			`ENABLE`
244			`optional`
245
246
247			`RESET`
248			`illegal`
249
250
251			`optional`
252			`1`
253			`out`
254
255
256			`optional`
257			`1`
258			`in`
259
260
261
262	131	jt_eaton
263
264
265
266
267
268
269
270	135	jt_eaton
271			`tdi`
272
273
274			`CLOCK`
275			`illegal`
276
277
278			`ENABLE`
279			`illegal`
280
281
282			`RESET`
283			`illegal`
284
285
286			`optional`
287			`1`
288			`out`
289
290
291			`optional`
292			`1`
293			`in`
294
295
296
297	131	jt_eaton
298
299
300
301
302	135	jt_eaton
303			`tdo`
304
305
306			`CLOCK`
307			`illegal`
308
309
310			`ENABLE`
311			`illegal`
312
313
314			`RESET`
315			`illegal`
316
317
318			`optional`
319			`1`
320			`in`
321
322
323			`optional`
324			`1`
325			`out`
326
327
328
329	131	jt_eaton
330
331
332
333
334
335	135	jt_eaton
336
337	131	jt_eaton
338
339
340
341
342
343
344
345