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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [verilog/] [jtag_classic_sync.v] - Blame information for rev 131

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/**********************************************************************/
/*                                                                    */
/*                                                                    */
/*   Copyright (c) 2012 Ouabache Design Works                         */
/*                                                                    */
/*          All Rights Reserved Worldwide                             */
/*                                                                    */
/*   Licensed under the Apache License,Version2.0 (the'License');     */
/*   you may not use this file except in compliance with the License. */
/*   You may obtain a copy of the License at                          */
/*                                                                    */
/*       http://www.apache.org/licenses/LICENSE-2.0                   */
/*                                                                    */
/*   Unless required by applicable law or agreed to in                */
/*   writing, software distributed under the License is               */
/*   distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES              */
/*   OR CONDITIONS OF ANY KIND, either express or implied.            */
/*   See the License for the specific language governing              */
/*   permissions and limitations under the License.                   */
/**********************************************************************/
 
module
cde_jtag_classic_sync
#(parameter JTAG_SEL        = 1   // number of select signals
  )
 
 
(
 input wire             clk, // system clock
 
 
 input wire             update_dr_clk, // clock
 input wire             shiftcapture_dr_clk, // clock
 input wire             test_logic_reset, // async reset
 input wire             tdi, // scan-in of jtag_register
 input wire  [JTAG_SEL-1:0]      select, // '1' when jtag accessing this register 
 output wire [JTAG_SEL-1:0] tdo, // scan-out of jtag register
 input wire             capture_dr,
 input wire             shift_dr,
 
 
 output wire            syn_clk,
 output reg             syn_reset,
 input wire [JTAG_SEL-1:0]       syn_tdo_i, // scan-in of jtag_register
 output reg [JTAG_SEL-1:0]       syn_select, // '1' when jtag accessing this register 
 output reg             syn_tdi_o, // scan-out of jtag register
 output reg             syn_capture_dr,
 output reg             syn_shift_dr,
 output reg             syn_update_dr
 
);
 
 
 
   reg                    synced_reset;
 
   always@(posedge clk or posedge test_logic_reset  )
   if(test_logic_reset)
      begin
      synced_reset <= 1'b1;
      syn_reset    <= 1'b1;
      end
   else
      begin
      synced_reset <= test_logic_reset;
      syn_reset    <= synced_reset;
      end
 
 
   reg                    synced_shift_dr;
   reg                    synced_capture_dr;
 
 
 
 
   always@(posedge clk)
     if(!shiftcapture_dr_clk)
       begin
       synced_shift_dr    <= shift_dr ;
       synced_capture_dr  <= capture_dr ;
       end
 
     else
       begin
       synced_shift_dr    <= synced_shift_dr ;
       synced_capture_dr  <= synced_capture_dr ;
       end
 
 
   reg [1:0]  synced_shiftcapture_dr_clk;
 
 
   always@(posedge clk)
     synced_shiftcapture_dr_clk <= {synced_shiftcapture_dr_clk[0],shiftcapture_dr_clk};
 
 
   reg [1:0]  synced_update_dr_clk;
 
 
   always@(posedge clk)
     synced_update_dr_clk <= {synced_update_dr_clk[0],update_dr_clk};
 
 
 
   always@(posedge clk)
     if(synced_shiftcapture_dr_clk == 2'b01)
       begin
       syn_shift_dr      <= synced_shift_dr ;
       syn_capture_dr    <= synced_capture_dr ;
       end
     else
       begin
       syn_shift_dr      <= 1'b0 ;
       syn_capture_dr    <= 1'b0 ;
       end
 
 
 
   always@(posedge clk)
     if(synced_update_dr_clk == 2'b01)
       begin
       syn_update_dr      <= 1'b1 ;
       end
     else
       begin
       syn_update_dr      <= 1'b0 ;
       end
 
 
 
   always@(posedge clk)
     if(!shiftcapture_dr_clk && (shift_dr || capture_dr  ))
       begin
       syn_tdi_o         <= tdi ;
       end
 
     else
       begin
       syn_tdi_o         <= syn_tdi_o ;
       end
 
 
 
 
 
 
 
 
 
 
   always@(posedge clk)
     if(synced_update_dr_clk == 2'b01)
       begin
       syn_select      <= select;
       end
   else if(synced_shiftcapture_dr_clk == 2'b01)
       begin
       syn_select      <= select;
       end
 
     else
       begin
       syn_select      <= syn_select;
       end
 
 
 
 
 
 
 
 
   assign    syn_clk             = clk;
   assign    tdo                 = syn_tdo_i;
 
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	131	jt_eaton	`/**********************************************************************/`
2			`/* */`
3			`/* */`
4			`/* Copyright (c) 2012 Ouabache Design Works */`
5			`/* */`
6			`/* All Rights Reserved Worldwide */`
7			`/* */`
8			`/* Licensed under the Apache License,Version2.0 (the'License'); */`
9			`/* you may not use this file except in compliance with the License. */`
10			`/* You may obtain a copy of the License at */`
11			`/* */`
12			`/* http://www.apache.org/licenses/LICENSE-2.0 */`
13			`/* */`
14			`/* Unless required by applicable law or agreed to in */`
15			`/* writing, software distributed under the License is */`
16			`/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */`
17			`/* OR CONDITIONS OF ANY KIND, either express or implied. */`
18			`/* See the License for the specific language governing */`
19			`/* permissions and limitations under the License. */`
20			`/**********************************************************************/`
21
22			`module`
23			`cde_jtag_classic_sync`
24			`#(parameter JTAG_SEL = 1 // number of select signals`
25			`)`
26
27
28			`(`
29			`input wire clk, // system clock`
30
31
32			`input wire update_dr_clk, // clock`
33			`input wire shiftcapture_dr_clk, // clock`
34			`input wire test_logic_reset, // async reset`
35			`input wire tdi, // scan-in of jtag_register`
36			`input wire [JTAG_SEL-1:0] select, // '1' when jtag accessing this register`
37			`output wire [JTAG_SEL-1:0] tdo, // scan-out of jtag register`
38			`input wire capture_dr,`
39			`input wire shift_dr,`
40
41
42			`output wire syn_clk,`
43			`output reg syn_reset,`
44			`input wire [JTAG_SEL-1:0] syn_tdo_i, // scan-in of jtag_register`
45			`output reg [JTAG_SEL-1:0] syn_select, // '1' when jtag accessing this register`
46			`output reg syn_tdi_o, // scan-out of jtag register`
47			`output reg syn_capture_dr,`
48			`output reg syn_shift_dr,`
49			`output reg syn_update_dr`
50
51			`);`
52
53
54
55			`reg synced_reset;`
56
57			`always@(posedge clk or posedge test_logic_reset )`
58			`if(test_logic_reset)`
59			`begin`
60			`synced_reset <= 1'b1;`
61			`syn_reset <= 1'b1;`
62			`end`
63			`else`
64			`begin`
65			`synced_reset <= test_logic_reset;`
66			`syn_reset <= synced_reset;`
67			`end`
68
69
70			`reg synced_shift_dr;`
71			`reg synced_capture_dr;`
72
73
74
75
76			`always@(posedge clk)`
77			`if(!shiftcapture_dr_clk)`
78			`begin`
79			`synced_shift_dr <= shift_dr ;`
80			`synced_capture_dr <= capture_dr ;`
81			`end`
82
83			`else`
84			`begin`
85			`synced_shift_dr <= synced_shift_dr ;`
86			`synced_capture_dr <= synced_capture_dr ;`
87			`end`
88
89
90			`reg [1:0] synced_shiftcapture_dr_clk;`
91
92
93			`always@(posedge clk)`
94			`synced_shiftcapture_dr_clk <= {synced_shiftcapture_dr_clk[0],shiftcapture_dr_clk};`
95
96
97			`reg [1:0] synced_update_dr_clk;`
98
99
100			`always@(posedge clk)`
101			`synced_update_dr_clk <= {synced_update_dr_clk[0],update_dr_clk};`
102
103
104
105			`always@(posedge clk)`
106			`if(synced_shiftcapture_dr_clk == 2'b01)`
107			`begin`
108			`syn_shift_dr <= synced_shift_dr ;`
109			`syn_capture_dr <= synced_capture_dr ;`
110			`end`
111			`else`
112			`begin`
113			`syn_shift_dr <= 1'b0 ;`
114			`syn_capture_dr <= 1'b0 ;`
115			`end`
116
117
118
119			`always@(posedge clk)`
120			`if(synced_update_dr_clk == 2'b01)`
121			`begin`
122			`syn_update_dr <= 1'b1 ;`
123			`end`
124			`else`
125			`begin`
126			`syn_update_dr <= 1'b0 ;`
127			`end`
128
129
130
131			`always@(posedge clk)`
132			`if(!shiftcapture_dr_clk && (shift_dr \|\| capture_dr ))`
133			`begin`
134			`syn_tdi_o <= tdi ;`
135			`end`
136
137			`else`
138			`begin`
139			`syn_tdi_o <= syn_tdi_o ;`
140			`end`
141
142
143
144
145
146
147
148
149
150
151			`always@(posedge clk)`
152			`if(synced_update_dr_clk == 2'b01)`
153			`begin`
154			`syn_select <= select;`
155			`end`
156			`else if(synced_shiftcapture_dr_clk == 2'b01)`
157			`begin`
158			`syn_select <= select;`
159			`end`
160
161			`else`
162			`begin`
163			`syn_select <= syn_select;`
164			`end`
165
166
167
168
169
170
171
172
173			`assign syn_clk = clk;`
174			`assign tdo = syn_tdo_i;`
175
176
177
178
179
180			`endmodule`

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [verilog/] [jtag_classic_sync.v] - Blame information for rev 131