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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [verilog/] [jtag_sync.v] - Blame information for rev 131

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/**********************************************************************/
/*                                                                    */
/*                                                                    */
/*   Copyright (c) 2012 Ouabache Design Works                         */
/*                                                                    */
/*          All Rights Reserved Worldwide                             */
/*                                                                    */
/*   Licensed under the Apache License,Version2.0 (the'License');     */
/*   you may not use this file except in compliance with the License. */
/*   You may obtain a copy of the License at                          */
/*                                                                    */
/*       http://www.apache.org/licenses/LICENSE-2.0                   */
/*                                                                    */
/*   Unless required by applicable law or agreed to in                */
/*   writing, software distributed under the License is               */
/*   distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES              */
/*   OR CONDITIONS OF ANY KIND, either express or implied.            */
/*   See the License for the specific language governing              */
/*   permissions and limitations under the License.                   */
/**********************************************************************/
 
module
cde_jtag_sync
#(parameter JTAG_SEL        = 2   // number of select signals
  )
 
 
(
 input wire             clk, // system clock
 
 
 
 input wire             jtag_clk, // clock
 input wire             test_logic_reset, // async reset
 
 
 input wire             tdi, // scan-in of jtag_register
 input wire [JTAG_SEL-1:0]       select, // '1' when jtag accessing this register 
 output wire            tdo, // scan-out of jtag register
 input wire             capture_dr,
 input wire             shift_dr,
 input wire             update_dr,
 
 
 output wire            syn_clk,
 input wire             syn_tdi, // scan-in of jtag_register
 output wire [JTAG_SEL-1:0] syn_select, // '1' when jtag accessing this register 
 output wire            syn_tdo, // scan-out of jtag register
 output wire            syn_capture_dr,
 output wire            syn_shift_dr,
 output wire            syn_update_dr
 
);
 
   assign    syn_clk             = clk;
   assign    syn_select          = select;
   assign    syn_tdo             = tdi;
   assign    tdo                 = syn_tdi;
   assign    syn_capture_dr      = capture_dr;
   assign    syn_shift_dr        = shift_dr  ;
   assign    syn_update_dr       = update_dr;
 
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	131	jt_eaton	`/**********************************************************************/`
2			`/* */`
3			`/* */`
4			`/* Copyright (c) 2012 Ouabache Design Works */`
5			`/* */`
6			`/* All Rights Reserved Worldwide */`
7			`/* */`
8			`/* Licensed under the Apache License,Version2.0 (the'License'); */`
9			`/* you may not use this file except in compliance with the License. */`
10			`/* You may obtain a copy of the License at */`
11			`/* */`
12			`/* http://www.apache.org/licenses/LICENSE-2.0 */`
13			`/* */`
14			`/* Unless required by applicable law or agreed to in */`
15			`/* writing, software distributed under the License is */`
16			`/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */`
17			`/* OR CONDITIONS OF ANY KIND, either express or implied. */`
18			`/* See the License for the specific language governing */`
19			`/* permissions and limitations under the License. */`
20			`/**********************************************************************/`
21
22			`module`
23			`cde_jtag_sync`
24			`#(parameter JTAG_SEL = 2 // number of select signals`
25			`)`
26
27
28			`(`
29			`input wire clk, // system clock`
30
31
32
33			`input wire jtag_clk, // clock`
34			`input wire test_logic_reset, // async reset`
35
36
37			`input wire tdi, // scan-in of jtag_register`
38			`input wire [JTAG_SEL-1:0] select, // '1' when jtag accessing this register`
39			`output wire tdo, // scan-out of jtag register`
40			`input wire capture_dr,`
41			`input wire shift_dr,`
42			`input wire update_dr,`
43
44
45			`output wire syn_clk,`
46			`input wire syn_tdi, // scan-in of jtag_register`
47			`output wire [JTAG_SEL-1:0] syn_select, // '1' when jtag accessing this register`
48			`output wire syn_tdo, // scan-out of jtag register`
49			`output wire syn_capture_dr,`
50			`output wire syn_shift_dr,`
51			`output wire syn_update_dr`
52
53			`);`
54
55			`assign syn_clk = clk;`
56			`assign syn_select = select;`
57			`assign syn_tdo = tdi;`
58			`assign tdo = syn_tdi;`
59			`assign syn_capture_dr = capture_dr;`
60			`assign syn_shift_dr = shift_dr ;`
61			`assign syn_update_dr = update_dr;`
62
63
64
65
66
67			`endmodule`

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [verilog/] [jtag_sync.v] - Blame information for rev 131