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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_classic_rpc_reg.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
jtag
classic_rpc_reg  default
 
 
 
 
 

 
 
 jtag
  
  
    
 
      
        test_logic_reset
        test_logic_reset
      
 
      
        capture_dr
        capture_dr
      
 
      
        shift_dr
        shift_dr
      
 
      
        update_dr_clk
        update_dr_clk
      
 
 
      
        tdi
        tdi
      
 
      
        tdo
        tdo
      
 
      
        select
        select
      
 
 
      
        shiftcapture_dr_clk
        shiftcapture_dr_clk
      
 
 
 
    
 
 

 
 
 
 
 

 
   
      fs-sim
 
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
    
 
 

 
 
 
 
 

       
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
      
 
 
 

BITS16
RESET_VALUE'h0

 

 
 
 
 
capture_value
wire
in
BITS-10

 
 
update_value
wire
out
BITS-10

 
 
 
 

 

 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_classic_rpc_reg.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`jtag`
15			`classic_rpc_reg default`
16
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24			`jtag`
25
26
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30			`test_logic_reset`
31			`test_logic_reset`
32
33
34
35			`capture_dr`
36			`capture_dr`
37
38
39
40			`shift_dr`
41			`shift_dr`
42
43
44
45			`update_dr_clk`
46			`update_dr_clk`
47
48
49
50
51			`tdi`
52			`tdi`
53
54
55
56			`tdo`
57			`tdo`
58
59
60
61			`select`
62			`select`
63
64
65
66
67			`shiftcapture_dr_clk`
68			`shiftcapture_dr_clk`
69
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85			`fs-sim`
86
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89			`dest_dir`
90			`../verilog/`
91			`verilogSourcelibraryDir`
92
93
94
95
96
97
98			`fs-syn`
99
100
101			`dest_dir`
102			`../verilog/`
103			`verilogSourcelibraryDir`
104
105
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112
113			`fs-lint`
114
115			`dest_dir../verilog/`
116			`verilogSourcelibraryDir`
117
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135			`sim:Simulation:`
136			`Verilog`
137
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139			`fs-sim`
140
141
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144			`syn:Synthesis:`
145			`Verilog`
146
147
148			`fs-syn`
149
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151
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153
154
155			`doc`
156
157
158			`spirit:library="Testbench"`
159			`spirit:name="toolflow"`
160			`spirit:version="documentation"/>`
161
162			`:Documentation:`
163			`Verilog`
164
165
166
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169
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173
174			`BITS16`
175			`RESET_VALUE'h0`
176
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183			`capture_value`
184			`wire`
185			`in`
186			`BITS-10`
187
188
189
190			`update_value`
191			`wire`
192			`out`
193			`BITS-10`
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