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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_classic_sync.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
jtag
classic_sync  default
 
 

 
 
 jtag
  
  
    
 
      
        test_logic_reset
        test_logic_reset
      
 
      
        capture_dr
        capture_dr
      
 
      
        shift_dr
        shift_dr
      
 
      
        update_dr_clk
        update_dr_clk
      
 
 
      
        tdi
        tdi
      
 
      
        tdo
        tdo
     
      
      
 
      
        select
        select
      
 
 
      
        shiftcapture_dr_clk
        shiftcapture_dr_clk
        
        
      
 
 
 
    
 
 
 
 syn_jtag
  
  
    
 
 
 
      
        clk
        syn_clk
      
 
 
      
        test_logic_reset
        syn_reset
      
 
      
        capture_dr
        syn_capture_dr
      
 
      
        shift_dr
        syn_shift_dr
      
 
      
        update_dr
        syn_update_dr
      
 
 
      
        tdi
        syn_tdi_o
  
      
 
      
        tdo
        syn_tdo_i
        
     
      
 
      
        select
        syn_select
      
 
 
 
    
 
 

 
 
 
 
 

       
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
 
      
 
 
 
 
 

 
clk
wire
in

 
 

 

 
 
 
 
 
 
 
 

 
   
      fs-sim
 
 
      
        dest_dir
        ../verilog/
        verilogSource
        libraryDir
      
 
  
 
 
   
      fs-syn
 
      
        dest_dir
        ../verilog/
        verilogSource
        libraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../verilog/
        verilogSource
        libraryDir
      
 
    
 
 
 
 

 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_classic_sync.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`jtag`
15			`classic_sync default`
16
17
18
19
20
21			`jtag`
22
23
24
25
26
27			`test_logic_reset`
28			`test_logic_reset`
29
30
31
32			`capture_dr`
33			`capture_dr`
34
35
36
37			`shift_dr`
38			`shift_dr`
39
40
41
42			`update_dr_clk`
43			`update_dr_clk`
44
45
46
47
48			`tdi`
49			`tdi`
50
51
52
53			`tdo`
54			`tdo`
55	133	jt_eaton
56	131	jt_eaton
57
58
59
60			`select`
61			`select`
62
63
64
65
66			`shiftcapture_dr_clk`
67			`shiftcapture_dr_clk`
68
69
70
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76
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78			`syn_jtag`
79
80
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82
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84
85
86			`clk`
87			`syn_clk`
88
89
90
91
92			`test_logic_reset`
93			`syn_reset`
94
95
96
97			`capture_dr`
98			`syn_capture_dr`
99
100
101
102			`shift_dr`
103			`syn_shift_dr`
104
105
106
107			`update_dr`
108			`syn_update_dr`
109
110
111
112
113			`tdi`
114			`syn_tdi_o`
115
116
117
118
119			`tdo`
120			`syn_tdo_i`
121	133	jt_eaton
122	131	jt_eaton
123
124
125
126			`select`
127			`syn_select`
128
129
130
131
132
133
134
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142
143
144
145
146			`sim:Simulation:`
147			`Verilog`
148
149
150			`fs-sim`
151
152
153
154
155			`syn:Synthesis:`
156			`Verilog`
157
158
159			`fs-syn`
160
161
162
163
164
165
166			`doc`
167
168
169			`spirit:library="Testbench"`
170			`spirit:name="toolflow"`
171			`spirit:version="documentation"/>`
172
173			`:Documentation:`
174			`Verilog`
175
176
177
178
179
180
181
182
183
184
185
186
187	133	jt_eaton
188	131	jt_eaton
189
190			`clk`
191			`wire`
192			`in`
193
194
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197
198
199
200
201
202
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204
205
206
207
208
209
210			`fs-sim`
211
212
213
214			`dest_dir`
215			`../verilog/`
216			`verilogSource`
217			`libraryDir`
218
219
220
221
222
223
224			`fs-syn`
225
226
227			`dest_dir`
228			`../verilog/`
229			`verilogSource`
230			`libraryDir`
231
232
233
234
235
236
237
238
239
240			`fs-lint`
241
242			`dest_dir`
243			`../verilog/`
244			`verilogSource`
245			`libraryDir`
246
247
248
249
250
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