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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_rpc_in_reg.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
jtag
rpc_in_reg  default
 

 
 
 
 
 
 

 
 

 
   
      fs-sim
 
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
 
    
 
      fs-lint
      
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
    
 
 
 

 
 
 
 
 
 
 

       
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 

BITS16
RESET_VALUE'h0

 

 
clk
wire
in

 
reset
wire
in

 
 
tdi
wire
in

 
select
wire
in

 
capture_dr
wire
in

 
shift_dr
wire
in

 
 
tdo
wire
out

 
 
capture_value
wire
in
BITS-10

 
 
 
 
 
 

 

 
 
 
 
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`jtag`
15			`rpc_in_reg default`
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30			`fs-sim`
31
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34			`dest_dir`
35			`../verilog/`
36			`verilogSourcelibraryDir`
37
38
39
40
41
42
43			`fs-syn`
44
45
46			`dest_dir`
47			`../verilog/`
48			`verilogSourcelibraryDir`
49
50
51
52
53
54
55
56
57
58
59			`fs-lint`
60
61			`dest_dir../verilog/`
62			`verilogSourcelibraryDir`
63
64
65
66
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69
70
71
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83			`sim:Simulation:`
84			`Verilog`
85
86
87			`fs-sim`
88
89
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91
92			`syn:Synthesis:`
93			`Verilog`
94
95
96			`fs-syn`
97
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101
102
103
104
105			`doc`
106
107
108			`spirit:library="Testbench"`
109			`spirit:name="toolflow"`
110			`spirit:version="documentation"/>`
111
112			`:Documentation:`
113			`Verilog`
114
115
116
117
118
119
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123			`BITS16`
124			`RESET_VALUE'h0`
125
126
127
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129			`clk`
130			`wire`
131			`in`
132
133
134			`reset`
135			`wire`
136			`in`
137
138
139
140			`tdi`
141			`wire`
142			`in`
143
144
145			`select`
146			`wire`
147			`in`
148
149
150			`capture_dr`
151			`wire`
152			`in`
153
154
155			`shift_dr`
156			`wire`
157			`in`
158
159
160
161			`tdo`
162			`wire`
163			`out`
164
165
166
167			`capture_value`
168			`wire`
169			`in`
170			`BITS-10`
171
172
173
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175
176
177
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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_rpc_in_reg.xml] - Blame information for rev 131