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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_tap.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
jtag
tap  default
 
 
 
 
 

 
 jtag
  
  
    
 
      
        test_logic_reset
        test_logic_reset_o
        reg
        
      
 
      
        capture_dr
        
        capture_dr_o
        reg
        
      
 
      
        shift_dr
        
        shift_dr_o
        reg
        
      
 
      
        update_dr_clk
        update_dr_clk_o
        wire
       
      
 
      
        tdi
        tdi_o
       wire
      
      
 
      
      tdo
      
      tdo_i
      JTAG_SEL-10
      
      
 
      
      select
      
      select_o
      JTAG_SEL-10
      
      
 
      
      shiftcapture_dr_clk
      
      shiftcapture_dr_clk_o
      
      
      
 
    
 
 
 
 
 
 tclk_pad
  
  
  
    
      
        pad_in
        tclk_pad_in
      
 
    
 
 
 
 tdi_pad
  
  
  
    
      
        pad_in
        tdi_pad_in
      
 
    
 
 
 
 tms_pad
  
  
  
    
      
        pad_in
        tms_pad_in
      
 
    
 
 
 
 trst_n_pad
  
  
  
    
      
        pad_in
        trst_n_pad_in
      
 
    
 
 
 
 
 
 tdo_pad
  
  
  
    
      
        pad_out
        tdo_pad_out
      
      
        pad_oe
        tdo_pad_oe
      
 
    
 
 
 

 
 
 
 
 
 
 
 
 
 

 
 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../verilog
    
    
      view
      sim
    
  

 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../verilog
    
    
      view
      syn
    
  

 
 
 

 
 
 
 
 
 
 
 
 
 
 

       
 
              
              Hierarchical
              
                                   spirit:library="cde"
                                   spirit:name="jtag"
                                   spirit:version="def.design"/>
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
 
 
             
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
 
      
 
 

JTAG_SEL2
INST_LENGTH4
INST_RETURN4'b1101
INST_RESET4'b1111
CHIP_ID_VAL32'h12345678
NUM_USER2
EXTEST4'b0000
USER8'b1010_1001
SAMPLE4'b0001
HIGHZ_MODE4'b0010
CHIP_ID_ACCESS4'b0011
CLAMP4'b1000
RPC_DATA4'b1010
RPC_ADD4'b1001
BYPASS4'b1111
 
 

 
 

 
 
 
 
tap_highz_mode
reg
out

 
bsr_output_mode
reg
out

 
bsr_tdo_i
wire
in

 
jtag_clk
wire
out

 
update_dr_o
reg
out

 
bsr_select_o
wire
out

 

 

 
 
 
 
 

 
 
 
 
   
      fs-sim
 
 
      
        
        ../verilog/jtag_tap
        verilogSourcemodule
      
 
      
        dest_dir
        ../verilog/sim/
        verilogSourcelibraryDir
      
 
   
 
 
   
      fs-syn
 
      
        
        ../verilog/SYNTHESYS
        verilogSourceinclude
      
 
 
 
 
      
        
        ../verilog/jtag_tap
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../verilog/syn/
        verilogSourcelibraryDir
      
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../verilog/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 
 
 

 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_tap.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`jtag`
15			`tap default`
16
17
18
19
20
21
22
23			`jtag`
24
25
26
27
28
29			`test_logic_reset`
30			`test_logic_reset_o`
31			`reg`
32
33
34
35
36			`capture_dr`
37
38			`capture_dr_o`
39			`reg`
40
41
42
43
44			`shift_dr`
45
46			`shift_dr_o`
47			`reg`
48
49
50
51
52			`update_dr_clk`
53			`update_dr_clk_o`
54			`wire`
55
56
57
58
59			`tdi`
60			`tdi_o`
61			`wire`
62
63
64
65
66			`tdo`
67
68			`tdo_i`
69			`JTAG_SEL-10`
70
71
72
73
74			`select`
75
76			`select_o`
77			`JTAG_SEL-10`
78
79
80
81
82			`shiftcapture_dr_clk`
83
84			`shiftcapture_dr_clk_o`
85
86
87
88
89
90
91
92
93
94
95			`tclk_pad`
96
97
98
99
100
101			`pad_in`
102			`tclk_pad_in`
103
104
105
106
107
108
109			`tdi_pad`
110
111
112
113
114
115			`pad_in`
116			`tdi_pad_in`
117
118
119
120
121
122
123			`tms_pad`
124
125
126
127
128
129			`pad_in`
130			`tms_pad_in`
131
132
133
134
135
136
137			`trst_n_pad`
138
139
140
141
142
143			`pad_in`
144			`trst_n_pad_in`
145
146
147
148
149
150
151
152
153			`tdo_pad`
154
155
156
157
158
159			`pad_out`
160			`tdo_pad_out`
161
162
163			`pad_oe`
164			`tdo_pad_oe`
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188			`gen_verilogLib_sim`
189			`105.0`
190			`none`
191			`:Simulation:`
192			`./tools/verilog/gen_verilogLib`
193
194
195			`dest_dir`
196			`../verilog`
197
198
199			`view`
200			`sim`
201
202
203
204
205
206
207			`gen_verilogLib_syn`
208			`105.0`
209			`none`
210			`:Synthesis:`
211			`./tools/verilog/gen_verilogLib`
212
213
214			`dest_dir`
215			`../verilog`
216
217
218			`view`
219			`syn`
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242			`Hierarchical`
243
244			`spirit:library="cde"`
245			`spirit:name="jtag"`
246			`spirit:version="def.design"/>`
247
248
249
250
251			`sim:Simulation:`
252			`Verilog`
253
254
255			`fs-sim`
256
257
258
259
260			`syn:Synthesis:`
261			`Verilog`
262
263
264			`fs-syn`
265
266
267
268
269
270
271
272
273			`doc`
274
275
276			`spirit:library="Testbench"`
277			`spirit:name="toolflow"`
278			`spirit:version="documentation"/>`
279
280			`:Documentation:`
281			`Verilog`
282
283
284
285
286
287
288
289
290
291
292
293			`JTAG_SEL2`
294			`INST_LENGTH4`
295			`INST_RETURN4'b1101`
296			`INST_RESET4'b1111`
297			`CHIP_ID_VAL32'h12345678`
298			`NUM_USER2`
299			`EXTEST4'b0000`
300			`USER8'b1010_1001`
301			`SAMPLE4'b0001`
302			`HIGHZ_MODE4'b0010`
303			`CHIP_ID_ACCESS4'b0011`
304			`CLAMP4'b1000`
305			`RPC_DATA4'b1010`
306			`RPC_ADD4'b1001`
307			`BYPASS4'b1111`
308
309
310
311
312
313
314
315
316
317
318			`tap_highz_mode`
319			`reg`
320			`out`
321
322
323			`bsr_output_mode`
324			`reg`
325			`out`
326
327
328			`bsr_tdo_i`
329			`wire`
330			`in`
331
332
333			`jtag_clk`
334			`wire`
335			`out`
336
337
338			`update_dr_o`
339			`reg`
340			`out`
341
342
343			`bsr_select_o`
344			`wire`
345			`out`
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362			`fs-sim`
363
364
365
366
367			`../verilog/jtag_tap`
368			`verilogSourcemodule`
369
370
371
372			`dest_dir`
373			`../verilog/sim/`
374			`verilogSourcelibraryDir`
375
376
377
378
379
380
381			`fs-syn`
382
383
384
385			`../verilog/SYNTHESYS`
386			`verilogSourceinclude`
387
388
389
390
391
392
393
394			`../verilog/jtag_tap`
395			`verilogSourcemodule`
396
397
398
399
400			`dest_dir`
401			`../verilog/syn/`
402			`verilogSourcelibraryDir`
403
404
405
406
407
408
409
410
411			`fs-lint`
412
413			`dest_dir`
414			`../verilog/syn/`
415			`verilogSourcelibraryDir`
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434