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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_tap.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
jtag
tap
 
 
 
 
 
 

 
  
  jtag
  
  
      
  
 
 
    
 
      
        test_logic_reset
        test_logic_reset_o
      
 
      
        capture_dr
        capture_dr_o
      
 
      
        shift_dr
        
        shift_dr_o
        
      
 
      
        update_dr_clk
        update_dr_clk_o
       
      
 
      
        tdi
        tdi_o
      
      
 
      
      tdo
      
      tdo_i
      
      
 
      
      select
      
      select_o
      
      
 
      
      shiftcapture_dr_clk
      
      shiftcapture_dr_clk_o
      
      
 
    
 
 
        
      
 
 
 
  
 
  
 
 
 
   aux_jtag
  
  
      
  
 
    
 
      
        test_logic_reset
        aux_test_logic_reset_o
        
      
 
      
        capture_dr
        
        aux_capture_dr_o
        
      
 
      
        shift_dr
        
        aux_shift_dr_o
        
      
 
      
        update_dr_clk
        aux_update_dr_clk_o
       
      
 
      
        tdi
        aux_tdi_o
      
      
 
      
      tdo
      
      aux_tdo_i
      
      
 
      
      select
      
      aux_select_o
      
      
 
      
      shiftcapture_dr_clk
      
      aux_shiftcapture_dr_clk_o
      
      
 
    
 
 
        
      
 
 
 
 
  
 
 
  
 
 
 
 
 tclk_pad
  
  
      
  
 
 
    
      
        pad_in
        tclk_pad_in
      
 
    
 
        
      
 
 
 
  
 
  
 
 
 tdi_pad
  
  
      
  
    
      
        pad_in
        tdi_pad_in
      
 
    
 
        
      
 
 
  
 
 
 
 
 
 
 tms_pad
  
  
      
  
    
      
        pad_in
        tms_pad_in
      
 
    
        
      
  
 
  
 
 
 trst_n_pad
  
 
  
      
  
 
 
    
      
        pad_in
        trst_n_pad_in
      
 
    
 
        
  
 
 
 
  
 
  
 
 
 
 
 tdo_pad
  
 
  
      
  
 
    
      
        pad_out
        tdo_pad_out
      
      
        pad_oe
        tdo_pad_oe
      
 
    
 
 
        
  
 
 
 
  
 
 
  
 
 

 
 
 
 
 
 
 
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      jtag_tap
    
  

 
 
 
 

 
 
 
 
 
 
 
 
 
 
 

 
 
 
 
 
 
 
                
                        
                                Hierarchical
                                
                        
                
 
 
 
 
  
 
              
              Hierarchical
              Hierarchical
              
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
 
 
             
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
 
      
 
 
 
 
 
 
 
 

INST_LENGTH4
INST_RETURN4'b1101
INST_RESET4'b1111
CHIP_ID_VAL32'h00000000
NUM_USER2
EXTEST4'b0000
USER8'b1010_1001
SAMPLE4'b0001
HIGHZ_MODE4'b0010
CHIP_ID_ACCESS4'b0011
CLAMP4'b1000
RPC_DATA4'b1010
RPC_ADD4'b1001
BYPASS4'b1111
 
 

 
 

 
 
tclk_pad_in
wire
in

 
tdi_pad_in
wire
in

 
 
tms_pad_in
wire
in

 
 
trst_n_pad_in
wire
in

 
 
tdo_pad_out
wire
out

 
 
tdo_pad_oe
wire
out

 
 
 
 
test_logic_reset_o
wire
out

 
 
 
capture_dr_o
wire
out

 
 
shift_dr_o
wire
out

 
update_dr_clk_o
wire
out

 
tdi_o
wire
out

 
 
select_o
wire
out

 
 
shiftcapture_dr_clk_o
wire
out

 
 
tdo_i
wire
in

 
 
 
aux_tdo_i
wire
in

 
 
aux_test_logic_reset_o
wire
out

 
aux_capture_dr_o
wire
out

 
 
aux_shift_dr_o
wire
out

 
aux_update_dr_clk_o
wire
out

 
aux_tdi_o
wire
out

 
 
aux_select_o
wire
out

 
 
aux_shiftcapture_dr_clk_o
wire
out

 
 
 
 
 
 
 
 
 
 
 
tap_highz_mode
wire
out

 
bsr_output_mode
wire
out

 
bsr_tdo_i
wire
in

 
jtag_clk
wire
out

 
update_dr_o
wire
out

 
bsr_select_o
wire
out

 

 

 
 
 
 
 
 

 
 
 
   
      fs-common
 
 
   
 
 
 
 
   
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/jtag_tap
        verilogSourcemodule
      
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
   
 
 
   
      fs-syn
 
      
        
        ../verilog/SYNTHESIS
        verilogSourceinclude
      
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
 
      
        
        ../verilog/common/jtag_tap
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 

 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_tap.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	131	jt_eaton
12	135	jt_eaton	`opencores.org`
13			`cde`
14			`jtag`
15			`tap`
16	131	jt_eaton
17
18
19
20
21
22	135	jt_eaton
23	131	jt_eaton
24	135	jt_eaton
25			`jtag`
26
27
28
29
30	131	jt_eaton
31
32	135	jt_eaton
33	131	jt_eaton
34	135	jt_eaton
35			`test_logic_reset`
36			`test_logic_reset_o`
37
38	131	jt_eaton
39	135	jt_eaton
40			`capture_dr`
41			`capture_dr_o`
42
43	131	jt_eaton
44	135	jt_eaton
45			`shift_dr`
46
47			`shift_dr_o`
48
49
50	131	jt_eaton
51	135	jt_eaton
52			`update_dr_clk`
53			`update_dr_clk_o`
54
55
56	131	jt_eaton
57	135	jt_eaton
58			`tdi`
59			`tdi_o`
60
61
62	131	jt_eaton
63	135	jt_eaton
64			`tdo`
65
66			`tdo_i`
67
68
69	131	jt_eaton
70	135	jt_eaton
71			`select`
72
73			`select_o`
74
75
76	131	jt_eaton
77	135	jt_eaton
78			`shiftcapture_dr_clk`
79
80			`shiftcapture_dr_clk_o`
81
82
83	131	jt_eaton
84	135	jt_eaton
85	131	jt_eaton
86	135	jt_eaton
87
88
89	133	jt_eaton
90
91
92	135	jt_eaton
93	133	jt_eaton
94	135	jt_eaton
95	133	jt_eaton
96
97	135	jt_eaton
98			`aux_jtag`
99
100
101
102
103	133	jt_eaton
104	135	jt_eaton
105	133	jt_eaton
106	135	jt_eaton
107			`test_logic_reset`
108			`aux_test_logic_reset_o`
109
110
111	133	jt_eaton
112	135	jt_eaton
113			`capture_dr`
114
115			`aux_capture_dr_o`
116
117
118	133	jt_eaton
119	135	jt_eaton
120			`shift_dr`
121
122			`aux_shift_dr_o`
123
124
125	133	jt_eaton
126	135	jt_eaton
127			`update_dr_clk`
128			`aux_update_dr_clk_o`
129
130
131	131	jt_eaton
132	135	jt_eaton
133			`tdi`
134			`aux_tdi_o`
135
136
137	131	jt_eaton
138	135	jt_eaton
139			`tdo`
140
141			`aux_tdo_i`
142
143
144	131	jt_eaton
145	135	jt_eaton
146			`select`
147
148			`aux_select_o`
149
150
151	131	jt_eaton
152	135	jt_eaton
153			`shiftcapture_dr_clk`
154
155			`aux_shiftcapture_dr_clk_o`
156
157
158	131	jt_eaton
159	135	jt_eaton
160	131	jt_eaton
161	135	jt_eaton
162
163
164	131	jt_eaton
165
166
167
168	135	jt_eaton
169	131	jt_eaton
170
171	135	jt_eaton
172	131	jt_eaton
173
174
175
176	135	jt_eaton	`tclk_pad`
177
178
179
180
181	131	jt_eaton
182
183	135	jt_eaton
184
185			`pad_in`
186			`tclk_pad_in`
187
188	131	jt_eaton
189	135	jt_eaton
190
191
192
193	131	jt_eaton
194
195
196	135	jt_eaton
197	131	jt_eaton
198	135	jt_eaton
199	131	jt_eaton
200
201	135	jt_eaton	`tdi_pad`
202
203
204
205
206
207
208			`pad_in`
209			`tdi_pad_in`
210
211	131	jt_eaton
212	135	jt_eaton
213
214
215
216	131	jt_eaton
217
218	135	jt_eaton
219
220
221	131	jt_eaton
222
223	135	jt_eaton
224	131	jt_eaton
225	135	jt_eaton	`tms_pad`
226
227
228
229
230
231
232			`pad_in`
233			`tms_pad_in`
234
235	131	jt_eaton
236	135	jt_eaton
237
238
239
240	131	jt_eaton
241	135	jt_eaton
242	131	jt_eaton
243
244	135	jt_eaton	`trst_n_pad`
245
246	131	jt_eaton
247	135	jt_eaton
248
249
250	131	jt_eaton
251
252	135	jt_eaton
253
254			`pad_in`
255			`trst_n_pad_in`
256
257	131	jt_eaton
258	135	jt_eaton
259
260
261
262	131	jt_eaton
263
264
265	135	jt_eaton
266	131	jt_eaton
267	135	jt_eaton
268	131	jt_eaton
269
270
271
272	135	jt_eaton	`tdo_pad`
273
274	131	jt_eaton
275	135	jt_eaton
276
277
278
279
280
281			`pad_out`
282			`tdo_pad_out`
283
284
285			`pad_oe`
286			`tdo_pad_oe`
287
288	131	jt_eaton
289	135	jt_eaton
290	134	jt_eaton
291	135	jt_eaton
292
293
294
295
296	134	jt_eaton
297	135	jt_eaton
298	134	jt_eaton
299
300	135	jt_eaton
301	134	jt_eaton
302	131	jt_eaton
303	135	jt_eaton
304	131	jt_eaton
305
306
307
308
309
310
311
312
313
314	135	jt_eaton
315	131	jt_eaton
316
317
318
319	135	jt_eaton
320			`gen_verilog`
321			`104.0`
322			`none`
323			`:common:`
324			`tools/verilog/gen_verilog`
325
326
327			`destination`
328			`jtag_tap`
329
330
331
332	131	jt_eaton
333
334
335
336	135	jt_eaton
337	131	jt_eaton
338
339
340
341
342
343
344
345
346
347
348	135	jt_eaton
349	131	jt_eaton
350
351
352	134	jt_eaton
353	131	jt_eaton
354
355
356	135	jt_eaton
357
358			`Hierarchical`
359
360
361
362	131	jt_eaton
363
364	135	jt_eaton
365	131	jt_eaton
366	135	jt_eaton
367	131	jt_eaton
368	135	jt_eaton
369			`Hierarchical`
370			`Hierarchical`
371
372	131	jt_eaton
373	135	jt_eaton
374			`verilog`
375
376
377			`ipxact:library="Testbench"`
378			`ipxact:name="toolflow"`
379			`ipxact:version="verilog"/>`
380
381
382	131	jt_eaton
383
384
385	135	jt_eaton
386			`common:common:`
387			`Verilog`
388
389
390			`fs-common`
391
392
393	131	jt_eaton
394
395
396	135	jt_eaton
397			`sim:Simulation:`
398			`Verilog`
399
400
401			`fs-sim`
402
403
404	131	jt_eaton
405	135	jt_eaton
406			`syn:Synthesis:`
407			`Verilog`
408
409
410			`fs-syn`
411
412
413	131	jt_eaton
414
415
416
417
418	135	jt_eaton
419			`doc`
420
421
422			`ipxact:library="Testbench"`
423			`ipxact:name="toolflow"`
424			`ipxact:version="documentation"/>`
425
426			`:Documentation:`
427			`Verilog`
428
429	131	jt_eaton
430
431
432
433
434
435	135	jt_eaton
436	131	jt_eaton
437
438
439
440
441	134	jt_eaton
442
443
444	135	jt_eaton
445			`INST_LENGTH4`
446			`INST_RETURN4'b1101`
447			`INST_RESET4'b1111`
448			`CHIP_ID_VAL32'h00000000`
449			`NUM_USER2`
450			`EXTEST4'b0000`
451			`USER8'b1010_1001`
452			`SAMPLE4'b0001`
453			`HIGHZ_MODE4'b0010`
454			`CHIP_ID_ACCESS4'b0011`
455			`CLAMP4'b1000`
456			`RPC_DATA4'b1010`
457			`RPC_ADD4'b1001`
458			`BYPASS4'b1111`
459	134	jt_eaton
460
461	135	jt_eaton
462	134	jt_eaton
463
464	135	jt_eaton
465	134	jt_eaton
466
467	135	jt_eaton	`tclk_pad_in`
468			`wire`
469			`in`
470
471	134	jt_eaton
472	135	jt_eaton	`tdi_pad_in`
473			`wire`
474			`in`
475
476	134	jt_eaton
477
478	135	jt_eaton	`tms_pad_in`
479			`wire`
480			`in`
481
482	134	jt_eaton
483
484	135	jt_eaton	`trst_n_pad_in`
485			`wire`
486			`in`
487
488	134	jt_eaton
489
490	135	jt_eaton	`tdo_pad_out`
491			`wire`
492			`out`
493
494	134	jt_eaton
495
496	135	jt_eaton	`tdo_pad_oe`
497			`wire`
498			`out`
499
500
501
502
503
504			`test_logic_reset_o`
505			`wire`
506			`out`
507
508
509
510
511			`capture_dr_o`
512			`wire`
513			`out`
514
515
516
517			`shift_dr_o`
518			`wire`
519			`out`
520
521
522			`update_dr_clk_o`
523			`wire`
524			`out`
525
526
527			`tdi_o`
528			`wire`
529			`out`
530
531
532
533			`select_o`
534			`wire`
535			`out`
536
537
538
539			`shiftcapture_dr_clk_o`
540			`wire`
541			`out`
542
543
544
545			`tdo_i`
546			`wire`
547			`in`
548
549
550
551
552			`aux_tdo_i`
553			`wire`
554			`in`
555
556
557
558			`aux_test_logic_reset_o`
559			`wire`
560			`out`
561
562
563			`aux_capture_dr_o`
564			`wire`
565			`out`
566
567
568
569			`aux_shift_dr_o`
570			`wire`
571			`out`
572
573
574			`aux_update_dr_clk_o`
575			`wire`
576			`out`
577
578
579			`aux_tdi_o`
580			`wire`
581			`out`
582
583
584
585			`aux_select_o`
586			`wire`
587			`out`
588
589
590
591			`aux_shiftcapture_dr_clk_o`
592			`wire`
593			`out`
594
595
596
597
598
599
600
601
602
603
604
605
606			`tap_highz_mode`
607			`wire`
608			`out`
609
610
611			`bsr_output_mode`
612			`wire`
613			`out`
614
615
616			`bsr_tdo_i`
617			`wire`
618			`in`
619
620
621			`jtag_clk`
622			`wire`
623			`out`
624
625
626			`update_dr_o`
627			`wire`
628			`out`
629
630
631			`bsr_select_o`
632			`wire`
633			`out`
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650			`fs-common`
651
652
653
654
655
656
657
658
659			`fs-sim`
660
661
662
663			`../verilog/copyright`
664			`verilogSourceinclude`
665
666
667
668
669
670			`../verilog/common/jtag_tap`
671			`verilogSourcemodule`
672
673
674
675			`dest_dir`
676			`../views/sim/`
677			`verilogSourcelibraryDir`
678
679
680
681
682
683
684			`fs-syn`
685
686
687
688			`../verilog/SYNTHESIS`
689			`verilogSourceinclude`
690
691
692
693
694			`../verilog/copyright`
695			`verilogSourceinclude`
696
697
698
699
700
701
702			`../verilog/common/jtag_tap`
703			`verilogSourcemodule`
704
705
706
707
708			`dest_dir`
709			`../views/syn/`
710			`verilogSourcelibraryDir`
711
712
713
714
715
716
717
718
719			`fs-lint`
720
721			`dest_dir`
722			`../views/syn/`
723			`verilogSourcelibraryDir`
724
725
726
727
728
729
730
731
732
733
734
735
736
737