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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [rtl/] [xml/] [cde_mult_generic.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
mult
generic  default
 
 
 

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top.generic
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 
 
 

 
 
 

 
   
      fs-common
 
 
      
        ../verilog/top.generic
        verilogSourcefragment
      
 
 
  
 
 
   
      fs-sim
 
 
      
        ../verilog/common/top.generic
        verilogSourcemodule
      
 
 
      
        ../verilog/or1200_gmultp2_32x32.v
        verilogSourcemodule
      
 
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        ../verilog/common/top.generic
        verilogSourcemodule
      
 
      
        ../verilog/or1200_gmultp2_32x32.v
        verilogSourcemodule
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
 
    
 
      fs-lint
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 

 
 
 
 
 
 
 

       
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 

WIDTH32

 
 
 

 
clk
wire
in

 
reset
wire
in

 
 
 
 
 
 
a_in
wire
in
WIDTH-10

 
 
b_in
wire
in
WIDTH-10

 
 
alu_op_mul
wire
in

 
 
ex_freeze
wire
in

 
 
 
 
mul_prod_r
reg
out
2*WIDTH-10

 
 
mul_stall
wire
out

 
 
 
 

 

 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [rtl/] [xml/] [cde_mult_generic.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`mult`
15			`generic default`
16
17
18
19
20
21
22
23
24			`gen_verilog`
25			`104.0`
26			`none`
27			`common`
28			`./tools/verilog/gen_verilog`
29
30
31			`destination`
32			`top.generic`
33
34
35			`dest_dir`
36			`../verilog`
37
38
39
40
41
42
43
44
45			`gen_verilogLib_sim`
46			`105.0`
47			`none`
48			`:Simulation:`
49			`./tools/verilog/gen_verilogLib`
50
51
52			`dest_dir`
53			`../views`
54
55
56			`view`
57			`sim`
58
59
60
61
62
63
64
65			`gen_verilogLib_syn`
66			`105.0`
67			`none`
68			`:Synthesis:`
69			`./tools/verilog/gen_verilogLib`
70
71
72			`dest_dir`
73			`../views`
74
75
76			`view`
77			`syn`
78
79
80
81
82
83
84
85
86
87
88
89
90
91			`fs-common`
92
93
94
95			`../verilog/top.generic`
96			`verilogSourcefragment`
97
98
99
100
101
102
103
104			`fs-sim`
105
106
107
108			`../verilog/common/top.generic`
109			`verilogSourcemodule`
110
111
112
113
114			`../verilog/or1200_gmultp2_32x32.v`
115			`verilogSourcemodule`
116
117
118
119
120			`dest_dir../views/sim/`
121			`verilogSourcelibraryDir`
122
123
124
125
126
127
128			`fs-syn`
129
130
131			`../verilog/common/top.generic`
132			`verilogSourcemodule`
133
134
135
136			`../verilog/or1200_gmultp2_32x32.v`
137			`verilogSourcemodule`
138
139
140
141			`dest_dir../views/syn/`
142			`verilogSourcelibraryDir`
143
144
145
146
147
148
149
150
151
152
153			`fs-lint`
154
155			`dest_dir../views/syn/`
156			`verilogSourcelibraryDir`
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176			`commoncommon`
177
178			`Verilog`
179
180
181			`fs-common`
182
183
184
185
186			`sim:Simulation:`
187
188			`Verilog`
189
190
191			`fs-sim`
192
193
194
195
196
197
198			`syn:Synthesis:`
199
200			`Verilog`
201
202
203			`fs-syn`
204
205
206
207
208
209
210			`doc`
211
212
213			`spirit:library="Testbench"`
214			`spirit:name="toolflow"`
215			`spirit:version="documentation"/>`
216
217			`:Documentation:`
218			`Verilog`
219
220
221
222
223
224
225
226
227
228			`WIDTH32`
229
230
231
232
233
234
235			`clk`
236			`wire`
237			`in`
238
239
240			`reset`
241			`wire`
242			`in`
243
244
245
246
247
248
249
250			`a_in`
251			`wire`
252			`in`
253			`WIDTH-10`
254
255
256
257			`b_in`
258			`wire`
259			`in`
260			`WIDTH-10`
261
262
263
264			`alu_op_mul`
265			`wire`
266			`in`
267
268
269
270			`ex_freeze`
271			`wire`
272			`in`
273
274
275
276
277
278			`mul_prod_r`
279			`reg`
280			`out`
281			`2*WIDTH-10`
282
283
284
285			`mul_stall`
286			`wire`
287			`out`
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
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