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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [rtl/] [xml/] [cde_mult_generic.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
mult
generic  default
 
 
 

 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      configuration
      default
    
    
      dest_dir
      io_ports
    
  

 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top.generic
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 
 
 

 
 
 

 
   
      fs-common
 
 
      
        ../verilog/top.generic
        verilogSourcefragment
      
 
 
  
 
 
   
      fs-sim
 
 
      
        ../verilog/common/top.generic
        verilogSourcemodule
      
 
 
      
        ../verilog/or1200_gmultp2_32x32.v
        verilogSourcemodule
      
 
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        ../verilog/common/top.generic
        verilogSourcemodule
      
 
      
        ../verilog/or1200_gmultp2_32x32.v
        verilogSourcemodule
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
 
    
 
      fs-lint
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 

 
 
 
 
 
 
 

       
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 

 
clk
wire
in

 
reset
wire
in

 
 
 
 
 
 
a_in
wire
in
WIDTH-10

 
 
b_in
wire
in
WIDTH-10

 
 
alu_op_mul
wire
in

 
 
ex_freeze
wire
in

 
 
 
 
mul_prod_r
reg
out
2*WIDTH-10

 
 
mul_stall
wire
out

 
 
 
 

 

 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [rtl/] [xml/] [cde_mult_generic.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`mult`
15			`generic default`
16
17
18
19
20
21	133	jt_eaton
22			`elab_verilog`
23			`102.1`
24			`none`
25			`:Simulation:`
26			`./tools/verilog/elab_verilog`
27
28
29			`configuration`
30			`default`
31
32
33			`dest_dir`
34			`io_ports`
35
36
37
38	131	jt_eaton
39
40
41			`gen_verilog`
42			`104.0`
43			`none`
44			`common`
45			`./tools/verilog/gen_verilog`
46
47
48			`destination`
49			`top.generic`
50
51
52			`dest_dir`
53			`../verilog`
54
55
56
57
58
59
60
61
62			`gen_verilogLib_sim`
63			`105.0`
64			`none`
65			`:Simulation:`
66			`./tools/verilog/gen_verilogLib`
67
68
69			`dest_dir`
70			`../views`
71
72
73			`view`
74			`sim`
75
76
77
78
79
80
81
82			`gen_verilogLib_syn`
83			`105.0`
84			`none`
85			`:Synthesis:`
86			`./tools/verilog/gen_verilogLib`
87
88
89			`dest_dir`
90			`../views`
91
92
93			`view`
94			`syn`
95
96
97
98
99
100
101
102
103
104
105
106
107
108			`fs-common`
109
110
111
112			`../verilog/top.generic`
113			`verilogSourcefragment`
114
115
116
117
118
119
120
121			`fs-sim`
122
123
124
125			`../verilog/common/top.generic`
126			`verilogSourcemodule`
127
128
129
130
131			`../verilog/or1200_gmultp2_32x32.v`
132			`verilogSourcemodule`
133
134
135
136
137			`dest_dir../views/sim/`
138			`verilogSourcelibraryDir`
139
140
141
142
143
144
145			`fs-syn`
146
147
148			`../verilog/common/top.generic`
149			`verilogSourcemodule`
150
151
152
153			`../verilog/or1200_gmultp2_32x32.v`
154			`verilogSourcemodule`
155
156
157
158			`dest_dir../views/syn/`
159			`verilogSourcelibraryDir`
160
161
162
163
164
165
166
167
168
169
170			`fs-lint`
171
172			`dest_dir../views/syn/`
173			`verilogSourcelibraryDir`
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193			`commoncommon`
194
195			`Verilog`
196
197
198			`fs-common`
199
200
201
202
203			`sim:Simulation:`
204
205			`Verilog`
206
207
208			`fs-sim`
209
210
211
212
213
214
215			`syn:Synthesis:`
216
217			`Verilog`
218
219
220			`fs-syn`
221
222
223
224
225
226
227			`doc`
228
229
230			`spirit:library="Testbench"`
231			`spirit:name="toolflow"`
232			`spirit:version="documentation"/>`
233
234			`:Documentation:`
235			`Verilog`
236
237
238
239
240
241
242
243
244
245
246
247
248			`clk`
249			`wire`
250			`in`
251
252
253			`reset`
254			`wire`
255			`in`
256
257
258
259
260
261
262
263			`a_in`
264			`wire`
265			`in`
266			`WIDTH-10`
267
268
269
270			`b_in`
271			`wire`
272			`in`
273			`WIDTH-10`
274
275
276
277			`alu_op_mul`
278			`wire`
279			`in`
280
281
282
283			`ex_freeze`
284			`wire`
285			`in`
286
287
288
289
290
291			`mul_prod_r`
292			`reg`
293			`out`
294			`2*WIDTH-10`
295
296
297
298			`mul_stall`
299			`wire`
300			`out`
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317