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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [rtl/] [xml/] [cde_mult_serial.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
mult
serial  default
 
 
 

 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top.serial
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 
 
 

 
 
 

 
   
      fs-common
 
      
        ../verilog/top.serial
        verilogSourcefragment
      
 
  
 
 
   
      fs-sim
 
      
        ../verilog/common/top.serial
        verilogSourcemodule
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        ../verilog/common/top.serial
        verilogSourcemodule
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 

 
 
 
 
 
 
 

       
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
             
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
 
      
 
 
 

WIDTH32

 
 
 

 
clk
wire
in

 
reset
wire
in

 
 
 
 
 
 
a_in
wire
in
WIDTH-10

 
 
b_in
wire
in
WIDTH-10

 
 
alu_op_mul
wire
in

 
 
ex_freeze
wire
in

 
 
 
 
mul_prod_r
reg
out
2*WIDTH-10

 
 
mul_stall
wire
out

 
 
 
 

 

 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [rtl/] [xml/] [cde_mult_serial.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`mult`
15			`serial default`
16
17
18
19
20
21
22
23			`gen_verilog`
24			`104.0`
25			`none`
26			`common`
27			`./tools/verilog/gen_verilog`
28
29
30			`destination`
31			`top.serial`
32
33
34			`dest_dir`
35			`../verilog`
36
37
38
39
40
41
42
43
44			`gen_verilogLib_sim`
45			`105.0`
46			`none`
47			`:Simulation:`
48			`./tools/verilog/gen_verilogLib`
49
50
51			`dest_dir`
52			`../views`
53
54
55			`view`
56			`sim`
57
58
59
60
61
62
63			`gen_verilogLib_syn`
64			`105.0`
65			`none`
66			`:Synthesis:`
67			`./tools/verilog/gen_verilogLib`
68
69
70			`dest_dir`
71			`../views`
72
73
74			`view`
75			`syn`
76
77
78
79
80
81
82
83
84
85
86
87
88
89			`fs-common`
90
91
92			`../verilog/top.serial`
93			`verilogSourcefragment`
94
95
96
97
98
99
100			`fs-sim`
101
102
103			`../verilog/common/top.serial`
104			`verilogSourcemodule`
105
106
107
108			`dest_dir../views/sim/`
109			`verilogSourcelibraryDir`
110
111
112
113
114
115
116			`fs-syn`
117
118
119			`../verilog/common/top.serial`
120			`verilogSourcemodule`
121
122
123
124			`dest_dir../views/syn/`
125			`verilogSourcelibraryDir`
126
127
128
129
130
131
132
133
134
135			`fs-lint`
136
137			`dest_dir../views/syn/`
138			`verilogSourcelibraryDir`
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158			`commoncommon`
159
160			`Verilog`
161
162
163			`fs-common`
164
165
166
167
168
169			`sim:Simulation:`
170
171			`Verilog`
172
173
174			`fs-sim`
175
176
177
178
179
180
181			`syn:Synthesis:`
182
183			`Verilog`
184
185
186			`fs-syn`
187
188
189
190
191
192
193			`doc`
194
195
196			`spirit:library="Testbench"`
197			`spirit:name="toolflow"`
198			`spirit:version="documentation"/>`
199
200			`:Documentation:`
201			`Verilog`
202
203
204
205
206
207
208
209
210
211
212
213
214			`WIDTH32`
215
216
217
218
219
220
221			`clk`
222			`wire`
223			`in`
224
225
226			`reset`
227			`wire`
228			`in`
229
230
231
232
233
234
235
236			`a_in`
237			`wire`
238			`in`
239			`WIDTH-10`
240
241
242
243			`b_in`
244			`wire`
245			`in`
246			`WIDTH-10`
247
248
249
250			`alu_op_mul`
251			`wire`
252			`in`
253
254
255
256			`ex_freeze`
257			`wire`
258			`in`
259
260
261
262
263
264			`mul_prod_r`
265			`reg`
266			`out`
267			`2*WIDTH-10`
268
269
270
271			`mul_stall`
272			`wire`
273			`out`
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
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290