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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [sim/] [testbenches/] [verilog/] [top.64] - Blame information for rev 131

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Line No. Rev Author Line
1 131 jt_eaton
 
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io_probe_in
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 #(.MESG         ("multiply error"),
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   .WIDTH        (32)
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  )
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rdata_tpb
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  (
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  .clk            (  clk        ),
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  .expected_value (  mul_prod_exp[31:0]  ),
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  .mask           (  {32{mask}} ),
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  .signal         (  mul_prod_r[31:0]      )
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  );
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`ifndef SYNTHESYS
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  task u_cmp;
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    input  [31:0] a_in;
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    input  [31:0] b_in;
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    input  [31:0] exp;
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     begin
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      test.a_in <= a_in;
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      test.b_in <= b_in;
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      test.mul_prod_exp <= exp;
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      test.alu_op_mul  <= 1'b1;
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      test.ex_freeze    <= 1'b1;
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      test.cg.next(1);
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      while(mul_stall)        test.cg.next(1);
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      test.mask  <= 1'b1;
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      $display("%t %m   cycle %x %x %x",$realtime,a_in,b_in,exp );
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      test.alu_op_mul  <= 1'b0;
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      test.ex_freeze   <= 1'b0;
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      test.cg.next(1);
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      test.mask  <= 1'b0;
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   end
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  endtask
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`endif
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assign STOP = 1'b0;
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assign BAD = 1'b0;

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