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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [sim/] [testbenches/] [xml/] [cde_mult_generic_tb.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
mult
generic_tb
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top.generic_tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 

 
 
 
 
 
 
 
 

       
 
              
              Params
              
              
                                   spirit:library="cde"
                                   spirit:name="mult"
                                   spirit:version="generic_dut.params"/>
             
              
 
 
              
              Bfm
              
                                   spirit:library="cde"
                                   spirit:name="mult"
                                   spirit:version="bfm.design"/>
              
 
 
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 
 

 
 
 

 
 
   
      fs-common
 
      
        
        ../verilog/top
        verilogSourcefragment
      
 
   
 
 
 
 
 
   
      fs-sim
 
      
        
        ../verilog/common/top.generic_tb
        verilogSourcemodule
      
 
 
 
   
 
 
   
      fs-lint
 
      
        
        ../verilog/synthesys
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/top.generic_tb
        verilogSourcemodule
      
 
 
 
   
 
 
 
 

 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`mult`
15			`generic_tb`
16
17
18
19
20
21
22
23
24
25			`gen_verilog`
26			`104.0`
27			`none`
28			`common`
29			`./tools/verilog/gen_verilog`
30
31
32			`destination`
33			`top.generic_tb`
34
35
36			`dest_dir`
37			`../verilog`
38
39
40			`top`
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59			`Params`
60
61
62			`spirit:library="cde"`
63			`spirit:name="mult"`
64			`spirit:version="generic_dut.params"/>`
65
66
67
68
69
70			`Bfm`
71
72			`spirit:library="cde"`
73			`spirit:name="mult"`
74			`spirit:version="bfm.design"/>`
75
76
77
78
79
80
81			`icarus`
82
83
84			`spirit:library="Testbench"`
85			`spirit:name="toolflow"`
86			`spirit:version="icarus"/>`
87
88
89
90
91
92
93
94			`commoncommon`
95			`Verilog`
96
97
98			`fs-common`
99
100
101
102
103
104			`sim:Simulation:`
105			`Verilog`
106
107
108			`fs-sim`
109
110
111
112
113			`lint:Lint:`
114			`Verilog`
115
116
117			`fs-lint`
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134			`fs-common`
135
136
137
138			`../verilog/top`
139			`verilogSourcefragment`
140
141
142
143
144
145
146
147
148
149			`fs-sim`
150
151
152
153			`../verilog/common/top.generic_tb`
154			`verilogSourcemodule`
155
156
157
158
159
160
161
162
163			`fs-lint`
164
165
166
167			`../verilog/synthesys`
168			`verilogSourceinclude`
169
170
171
172
173
174			`../verilog/common/top.generic_tb`
175			`verilogSourcemodule`
176
177
178
179
180
181
182
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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [sim/] [testbenches/] [xml/] [cde_mult_generic_tb.xml] - Blame information for rev 133