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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [pad/] [rtl/] [xml/] [cde_pad_out_adhoc.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
pad
out_adhoc
 
 
 
 
 

 
 
 pad
  
  
      
  
          
            
        pad_out
        pad_out 
            
          
        
      
  
 
 

 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      pad_out_adhoc
    
  

 
 
 
 

 
 

 
 
 
                
                        
                                verilog
                                verilog
                                cde_pad_out_adhoc
                                
                                        
                                                WIDTH
                                                1
                                        
                                
                                
                                        fs-sim
                                
                        
                
 
 
 
 
  
 
                
                                rtl
                                verilog:Kactus2:
                                verilog
                        
 
             
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
                
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 

WIDTH1

 
 

 
 
 
pad_out
wire
out
WIDTH-10

 
 
adhoc_pad_out
wire
in
WIDTH-10

 
 
 
 
 
 
 
 

 

 
 
 
 
 
 
 

 
 
 
 
      fs-common
 
      
        
        ../verilog/pad_out_adhoc
        verilogSourcefragment
      
 
   
 
 
   
      fs-sim
 
   
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/pad_out_adhoc
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
  
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/pad_out_adhoc
        verilogSourcemodule
      
 
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 

 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [pad/] [rtl/] [xml/] [cde_pad_out_adhoc.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton
2
5
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`pad`
15			`out_adhoc`
16
17
18
19
20
21
22
23
24			`pad`
25
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27
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31			`pad_out`
32			`pad_out`
33
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42
43
44
45
46
47
48
49
50			`gen_verilog`
51			`104.0`
52			`none`
53			`:common:`
54			`tools/verilog/gen_verilog`
55
56
57			`destination`
58			`pad_out_adhoc`
59
60
61
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65
66
67
68
69
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71
72
73
74
75			`verilog`
76			`verilog`
77			`cde_pad_out_adhoc`
78
79
80			`WIDTH`
81			`1`
82
83
84
85			`fs-sim`
86
87
88
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93
94
95
96			`rtl`
97			`verilog:Kactus2:`
98			`verilog`
99
100
101
102			`verilog`
103
104
105			`ipxact:library="Testbench"`
106			`ipxact:name="toolflow"`
107			`ipxact:version="verilog"/>`
108
109
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113
114			`common:common:`
115			`Verilog`
116
117
118			`fs-common`
119
120
121
122
123
124			`sim:Simulation:`
125			`Verilog`
126
127
128			`fs-sim`
129
130
131
132
133			`syn:Synthesis:`
134			`Verilog`
135
136
137			`fs-syn`
138
139
140
141
142			`doc`
143
144
145			`ipxact:library="Testbench"`
146			`ipxact:name="toolflow"`
147			`ipxact:version="documentation"/>`
148
149			`:Documentation:`
150			`Verilog`
151
152
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157
158
159			`WIDTH1`
160
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164
165
166
167			`pad_out`
168			`wire`
169			`out`
170			`WIDTH-10`
171
172
173
174			`adhoc_pad_out`
175			`wire`
176			`in`
177			`WIDTH-10`
178
179
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182
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184
185
186
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202			`fs-common`
203
204
205
206			`../verilog/pad_out_adhoc`
207			`verilogSourcefragment`
208
209
210
211
212
213
214			`fs-sim`
215
216
217
218			`../verilog/copyright`
219			`verilogSourceinclude`
220
221
222
223
224
225			`../verilog/common/pad_out_adhoc`
226			`verilogSourcemodule`
227
228
229
230
231			`dest_dir`
232			`../views/sim/`
233			`verilogSourcelibraryDir`
234
235
236
237
238
239
240			`fs-syn`
241
242
243
244			`../verilog/copyright`
245			`verilogSourceinclude`
246
247
248
249
250
251			`../verilog/common/pad_out_adhoc`
252			`verilogSourcemodule`
253
254
255
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258			`dest_dir`
259			`../views/syn/`
260			`verilogSourcelibraryDir`
261
262
263
264
265
266
267
268
269
270			`fs-lint`
271
272			`dest_dir`
273			`../views/syn/`
274			`verilogSourcelibraryDir`
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