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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [serial/] [rtl/] [xml/] [cde_serial_rcvr.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
serial
rcvr  default
 

 
 
 
 
 
 

 
 
 
 
 
 

       
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
             
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 

WIDTH8
SIZE4
BREAK0
 

 

 
clk
wire
in

 
reset
wire
in

 
edge_enable
wire
in

 
parity_enable
wire
in

 
 
parity_type
wire
in

 
ser_in
wire
in

 
parity_force
wire
in

 
 
 
shift_buffer
reg
out
WIDTH-10

 
stop_cnt
reg
out

 
last_cnt
reg
out

 
parity_calc
reg
out

 
parity_samp
reg
out

 
frame_err
reg
out

 
 

 

 
 
 
 
 

 
   
      fs-sim
 
 
      
dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
    
 
 

 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`serial`
15			`rcvr default`
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35			`sim:Simulation:`
36			`Verilog`
37
38
39			`fs-sim`
40
41
42
43
44			`syn:Synthesis:`
45			`Verilog`
46
47
48			`fs-syn`
49
50
51
52
53
54
55			`doc`
56
57
58			`spirit:library="Testbench"`
59			`spirit:name="toolflow"`
60			`spirit:version="documentation"/>`
61
62			`:Documentation:`
63			`Verilog`
64
65
66
67
68
69
70
71
72
73			`WIDTH8`
74			`SIZE4`
75			`BREAK0`
76
77
78
79
80
81			`clk`
82			`wire`
83			`in`
84
85
86			`reset`
87			`wire`
88			`in`
89
90
91			`edge_enable`
92			`wire`
93			`in`
94
95
96			`parity_enable`
97			`wire`
98			`in`
99
100
101
102			`parity_type`
103			`wire`
104			`in`
105
106
107			`ser_in`
108			`wire`
109			`in`
110
111
112			`parity_force`
113			`wire`
114			`in`
115
116
117
118
119			`shift_buffer`
120			`reg`
121			`out`
122			`WIDTH-10`
123
124
125			`stop_cnt`
126			`reg`
127			`out`
128
129
130			`last_cnt`
131			`reg`
132			`out`
133
134
135			`parity_calc`
136			`reg`
137			`out`
138
139
140			`parity_samp`
141			`reg`
142			`out`
143
144
145			`frame_err`
146			`reg`
147			`out`
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162			`fs-sim`
163
164
165
166			`dest_dir`
167			`../verilog/`
168			`verilogSourcelibraryDir`
169
170
171
172
173
174
175			`fs-syn`
176
177
178			`dest_dir`
179			`../verilog/`
180			`verilogSourcelibraryDir`
181
182
183
184
185
186
187
188
189
190			`fs-lint`
191
192			`dest_dir../verilog/`
193			`verilogSourcelibraryDir`
194
195
196
197
198
199
200
201
202

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [serial/] [rtl/] [xml/] [cde_serial_rcvr.xml] - Blame information for rev 131