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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [componentCfg.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
 
opencores.org
cde
sram
 
 
3
_
_
_
VARIANT
 
 
 

 
/ip/sram/doc
sram/doc
 
 
 

 
  
   def
   Synchronous one-port ram
  
 
  
   dp
   Synchronous two-port ram with seperate read/write ports
  
 
  
   be
   Synchronous one-port ram with byte enable
  
 
 
 

 
 

 
  
   ADDR
   Number of address bits
  
 
  
   WIDTH
   Number of data bits
  
 
  
   WORDS
   Number of memory words. Must be fully addressable by ADDR address bits
  
 
  
   WRITETHRU
   If a read and write occur to the same address on the same cycle then 0 reads old data while 1 reads new
  
 
  
   DEFAULT
   Output read value if cs and rd are not both active 
  
 
 
 

 
 
 

 
  
   addr
   Memory address bits
  
 
  
   raddr
   Memory read address bits
  
 
  
   waddr
   Memory write address bits
  
 
  
   clk
   Active high clock
  
 
  
   cs
   Active high chip select
  
 
  
   rd
   Active high read enable
  
 
  
   wr
   Active high write enable
  
 
 
  
   be
   Active high byte enable
  
 
  
   rdata
   read data out
  
 
  
   wdata
   write data in
  
 
 

 
 
 
 
 
 
 
 

 
 
 
 
 

 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">`
9
10			`opencores.org`
11			`cde`
12			`sram`
13
14
15			`3`
16			`_`
17			`_`
18			`_`
19			`VARIANT`
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21
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23
24
25			`/ip/sram/doc`
26			`sram/doc`
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33			`def`
34			`Synchronous one-port ram`
35
36
37
38			`dp`
39			`Synchronous two-port ram with seperate read/write ports`
40
41
42
43			`be`
44			`Synchronous one-port ram with byte enable`
45
46
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55			`ADDR`
56			`Number of address bits`
57
58
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60			`WIDTH`
61			`Number of data bits`
62
63
64
65			`WORDS`
66			`Number of memory words. Must be fully addressable by ADDR address bits`
67
68
69
70			`WRITETHRU`
71			`If a read and write occur to the same address on the same cycle then 0 reads old data while 1 reads new`
72
73
74
75			`DEFAULT`
76			`Output read value if cs and rd are not both active`
77
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88			`addr`
89			`Memory address bits`
90
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93			`raddr`
94			`Memory read address bits`
95
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98			`waddr`
99			`Memory write address bits`
100
101
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103			`clk`
104			`Active high clock`
105
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108			`cs`
109			`Active high chip select`
110
111
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113			`rd`
114			`Active high read enable`
115
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118			`wr`
119			`Active high write enable`
120
121
122
123
124			`be`
125			`Active high byte enable`
126
127
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129			`rdata`
130			`read data out`
131
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134			`wdata`
135			`write data in`
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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [componentCfg.xml] - Blame information for rev 131