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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [xml/] [sram_word.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
sram
word
 
 
 

 
 slave_clk
  
 
 
  
      
  
          
            
        clk
        clk
            
          
        
      
  
 
 
 
 
 mem
  
 
  
      
        
    
 
      
        cs
        cs
        
      
 
      
        wr
        wr
        
      
 
      
        rd
        rd
        
      
 
      
        addr
        addr
        ADDR1
        
      
 
 
      
        wdata
        wdata
        150
        
      
 
 
      
        rdata
        rdata
        150
        
      
 
 
 
      
        be
        be
        10
        
      
    
 
 
        
      
 
  
  
 
 
 

 
 
 

 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      sram_word
    
  

 

 
 
 
 
 

 
 
 
 
 
                
                        
                                verilog
                                verilog
                                cde_sram_word
                                
                                        
                                                ADDR
                                                8
                                        
                                        
                                                WIDTH
                                                8
                                        
                                        
                                                WORDS
                                                256
                                        
                                        
                                                WRITETHRU
                                                1
                                        
                                
                                
                                        fs-sim
                                
                        
                
 
 
 
 
 
 
 
  
 
 
 
                        
                                rtl
                                verilog:Kactus2:
                                verilog
                        
 
 
             
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
             
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
 
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
      
 
 
 

 
 
 
 
 
 
 
clk
wire
in

 
cs
wire
in

 
wr
wire
in

 
rd
wire
in

 
 
 
addr
wire
in
ADDR1

 
 
 
 
wdata
wire
in
150

 
be
wire
in
10

 
rdata
reg
out
150

 
 
 

 

 
 
 
 
 
 
 

 
 
   
      fs-common
 
      
        
        ../verilog/sram_word
        verilogSourcefragment
      
 
 
 
 
 
   
 
 
   
      fs-sim
 
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
   
        
        ../verilog/common/sram_word
        verilogSourcemodule
      
 
 
       
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
  
 
 
   
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
 
   
        
        ../verilog/common/sram_word
        verilogSourcemodule
      
 
 
 
       
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
 
 
   
 
 
 
   
      fs-lint
 
 
       
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
 
 
   
 
 
 
 
 

 
 
 
 
 

 
 
 
  mem
  8
   
     mem
     0x0000
      
       mem
     
   
 
 
 

 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [xml/] [sram_word.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	131	jt_eaton
12	135	jt_eaton	`opencores.org`
13			`cde`
14			`sram`
15			`word`
16	131	jt_eaton
17
18
19	135	jt_eaton
20	131	jt_eaton
21	135	jt_eaton	`slave_clk`
22
23	131	jt_eaton
24
25	135	jt_eaton
26
27
28
29
30			`clk`
31			`clk`
32
33
34
35
36
37
38	131	jt_eaton
39
40	135	jt_eaton
41			`mem`
42
43	131	jt_eaton
44	135	jt_eaton
45
46
47
48	131	jt_eaton
49	135	jt_eaton
50			`cs`
51			`cs`
52
53
54	131	jt_eaton
55	135	jt_eaton
56			`wr`
57			`wr`
58
59
60	131	jt_eaton
61	135	jt_eaton
62			`rd`
63			`rd`
64
65
66	131	jt_eaton
67	135	jt_eaton
68			`addr`
69			`addr`
70			`ADDR1`
71
72
73	131	jt_eaton
74
75	135	jt_eaton
76			`wdata`
77			`wdata`
78			`150`
79
80
81	131	jt_eaton
82
83	135	jt_eaton
84			`rdata`
85			`rdata`
86			`150`
87
88
89	131	jt_eaton
90
91
92	135	jt_eaton
93			`be`
94			`be`
95			`10`
96
97
98
99
100	131	jt_eaton
101	135	jt_eaton
102
103	131	jt_eaton
104	135	jt_eaton
105
106	131	jt_eaton
107	135	jt_eaton
108	131	jt_eaton
109	135	jt_eaton
110	131	jt_eaton
111
112
113	135	jt_eaton
114	131	jt_eaton
115	135	jt_eaton
116			`gen_verilog`
117			`104.0`
118			`none`
119			`:common:`
120			`tools/verilog/gen_verilog`
121
122
123			`destination`
124			`sram_word`
125
126
127
128	131	jt_eaton
129	135	jt_eaton
130	131	jt_eaton
131
132
133
134
135	135	jt_eaton
136	134	jt_eaton
137
138
139
140
141	135	jt_eaton
142
143			`verilog`
144			`verilog`
145			`cde_sram_word`
146
147
148			`ADDR`
149			`8`
150
151
152			`WIDTH`
153			`8`
154
155
156			`WORDS`
157			`256`
158
159
160			`WRITETHRU`
161			`1`
162
163
164
165			`fs-sim`
166
167
168
169	134	jt_eaton
170	135	jt_eaton
171	134	jt_eaton
172
173	131	jt_eaton
174	134	jt_eaton
175
176	135	jt_eaton
177	134	jt_eaton
178
179	131	jt_eaton
180	135	jt_eaton
181			`rtl`
182			`verilog:Kactus2:`
183			`verilog`
184
185	131	jt_eaton
186	135	jt_eaton
187
188			`verilog`
189
190
191			`ipxact:library="Testbench"`
192			`ipxact:name="toolflow"`
193			`ipxact:version="verilog"/>`
194
195
196	131	jt_eaton
197	135	jt_eaton
198			`common:common:`
199			`Verilog`
200
201
202			`fs-common`
203
204
205	131	jt_eaton
206
207
208	135	jt_eaton
209			`sim:Simulation:`
210			`Verilog`
211
212
213			`fs-sim`
214
215
216	131	jt_eaton
217	135	jt_eaton
218			`syn:Synthesis:`
219			`Verilog`
220
221
222			`fs-syn`
223
224
225	131	jt_eaton
226
227	135	jt_eaton
228			`lint:Lint:`
229			`Verilog`
230
231
232			`fs-lint`
233
234
235	131	jt_eaton
236
237
238
239
240	135	jt_eaton
241			`doc`
242
243
244			`ipxact:library="Testbench"`
245			`ipxact:name="toolflow"`
246			`ipxact:version="documentation"/>`
247
248			`:Documentation:`
249			`Verilog`
250
251	131	jt_eaton
252
253
254
255	135	jt_eaton
256	131	jt_eaton
257
258
259	135	jt_eaton
260	131	jt_eaton
261
262
263
264
265
266
267	135	jt_eaton	`clk`
268			`wire`
269			`in`
270
271	131	jt_eaton
272	135	jt_eaton	`cs`
273			`wire`
274			`in`
275
276	131	jt_eaton
277	135	jt_eaton	`wr`
278			`wire`
279			`in`
280
281	131	jt_eaton
282	135	jt_eaton	`rd`
283			`wire`
284			`in`
285
286	131	jt_eaton
287
288
289	135	jt_eaton	`addr`
290			`wire`
291			`in`
292			`ADDR1`
293
294	131	jt_eaton
295
296
297
298	135	jt_eaton	`wdata`
299			`wire`
300			`in`
301			`150`
302
303	134	jt_eaton
304	135	jt_eaton	`be`
305			`wire`
306			`in`
307			`10`
308
309	134	jt_eaton
310	135	jt_eaton	`rdata`
311			`reg`
312			`out`
313			`150`
314
315	134	jt_eaton
316
317
318	135	jt_eaton
319	134	jt_eaton
320	135	jt_eaton
321	131	jt_eaton
322
323
324	134	jt_eaton
325
326
327	131	jt_eaton
328	135	jt_eaton
329	131	jt_eaton
330
331	135	jt_eaton
332			`fs-common`
333	131	jt_eaton
334	135	jt_eaton
335
336			`../verilog/sram_word`
337			`verilogSourcefragment`
338
339	131	jt_eaton
340
341
342
343	134	jt_eaton
344	135	jt_eaton
345	134	jt_eaton
346
347	135	jt_eaton
348			`fs-sim`
349	134	jt_eaton
350	131	jt_eaton
351	135	jt_eaton
352
353			`../verilog/copyright`
354			`verilogSourceinclude`
355
356	131	jt_eaton
357
358	135	jt_eaton
359
360			`../verilog/common/sram_word`
361			`verilogSourcemodule`
362
363	131	jt_eaton
364
365	135	jt_eaton
366			`dest_dir../views/sim/`
367			`verilogSourcelibraryDir`
368
369	131	jt_eaton
370
371
372	135	jt_eaton
373	131	jt_eaton
374
375	135	jt_eaton
376			`fs-syn`
377	131	jt_eaton
378	135	jt_eaton
379
380			`../verilog/copyright`
381			`verilogSourceinclude`
382
383	131	jt_eaton
384
385
386	135	jt_eaton
387
388			`../verilog/common/sram_word`
389			`verilogSourcemodule`
390
391	131	jt_eaton
392
393
394	135	jt_eaton
395			`dest_dir../views/syn/`
396			`verilogSourcelibraryDir`
397
398	131	jt_eaton
399
400
401
402	135	jt_eaton
403	131	jt_eaton
404
405
406	135	jt_eaton
407			`fs-lint`
408	131	jt_eaton
409
410	135	jt_eaton
411			`dest_dir../views/syn/`
412			`verilogSourcelibraryDir`
413
414	131	jt_eaton
415
416
417
418	135	jt_eaton
419	131	jt_eaton
420	135	jt_eaton
421
422
423
424
425
426
427
428
429
430
431
432
433
434			`mem`
435			`8`
436
437			`mem`
438			`0x0000`
439
440			`mem`
441
442
443
444
445
446
447
448
449
450
451