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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sync/] [rtl/] [xml/] [cde_sync_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
sync
def  default
 
 
 
 
 
 
 
 
 

 
 
              
 
      
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
              
 
 
 

WIDTH1
DEPTH2

 

 
clk
wire
in

 
 
data_in
wire
in
WIDTH-10

 
data_out
wire
out
WIDTH-10

 
 
 
 

 

 
 
 
 
 
 

 
   
      fs-sim
 
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
   
      fs-lint
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
   
 
 
 

 
 
 
 
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`sync`
15			`def default`
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31			`doc`
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34			`spirit:library="Testbench"`
35			`spirit:name="toolflow"`
36			`spirit:version="documentation"/>`
37
38			`:Documentation:`
39			`Verilog`
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51			`WIDTH1`
52			`DEPTH2`
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57			`clk`
58			`wire`
59			`in`
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63			`data_in`
64			`wire`
65			`in`
66			`WIDTH-10`
67
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69			`data_out`
70			`wire`
71			`out`
72			`WIDTH-10`
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90			`fs-sim`
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94			`dest_dir`
95			`../verilog/`
96			`verilogSourcelibraryDir`
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103			`fs-syn`
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106			`dest_dir`
107			`../verilog/`
108			`verilogSourcelibraryDir`
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117			`fs-lint`
118
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120			`dest_dir`
121			`../verilog/`
122			`verilogSourcelibraryDir`
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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sync/] [rtl/] [xml/] [cde_sync_def.xml] - Blame information for rev 131