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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sync/] [rtl/] [xml/] [cde_sync_with_reset.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
sync
with_reset  default
 

 
   
 
 
       
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
    
 

WIDTH1
DEPTH2

 

 
clk
wire
in

 
reset_n
wire
in

 
 
data_in
wire
in
WIDTH-10

 
data_out
wire
out
WIDTH-10

 
 
 
 

 

 
 
 
 

 
   
      fs-sim
 
 
      
      dest_dir
        ../verilog/
        verilogSource
        libraryDir
      
 
  
 
 
   
      fs-syn
 
      
dest_dir
        ../verilog/
        verilogSource
        libraryDir
      
 
 
 
   
 
 
   
      fs-lint
 
      
      dest_dir
        ../verilog/
        verilogSource
        libraryDir
      
 
   
 
 
 
 

 
 
 
 
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`sync`
15			`with_reset default`
16
17
18
19
20
21
22
23			`doc`
24
25
26			`spirit:library="Testbench"`
27			`spirit:name="toolflow"`
28			`spirit:version="documentation"/>`
29
30			`:Documentation:`
31			`Verilog`
32
33
34
35
36
37
38
39
40			`WIDTH1`
41			`DEPTH2`
42
43
44
45
46			`clk`
47			`wire`
48			`in`
49
50
51			`reset_n`
52			`wire`
53			`in`
54
55
56
57			`data_in`
58			`wire`
59			`in`
60			`WIDTH-10`
61
62
63			`data_out`
64			`wire`
65			`out`
66			`WIDTH-10`
67
68
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73
74
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76
77
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80
81
82			`fs-sim`
83
84
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86			`dest_dir`
87			`../verilog/`
88			`verilogSource`
89			`libraryDir`
90
91
92
93
94
95
96			`fs-syn`
97
98
99			`dest_dir`
100			`../verilog/`
101			`verilogSource`
102			`libraryDir`
103
104
105
106
107
108
109
110
111			`fs-lint`
112
113
114			`dest_dir`
115			`../verilog/`
116			`verilogSource`
117			`libraryDir`
118
119
120
121
122
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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sync/] [rtl/] [xml/] [cde_sync_with_reset.xml] - Blame information for rev 131