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Subversion Repositories socgen

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eval 'exec `which perl` -S $0 ${1+"$@"}'
   if 0;
 
#/**********************************************************************/
#/*                                                                    */
#/*             -------                                                */
#/*            /   SOC  \                                              */
#/*           /    GEN   \                                             */
#/*          /    TOOL    \                                            */
#/*          ==============                                            */
#/*          |            |                                            */
#/*          |____________|                                            */
#/*                                                                    */
#/*  convert verilog file(s) to a geda symbol                          */
#/*                                                                    */
#/*                                                                    */
#/*  Author(s):                                                        */
#/*      - John Eaton, jt_eaton@opencores.org                          */
#/*                                                                    */
#/**********************************************************************/
#/*                                                                    */
#/*    Copyright (C) <2010>                     */
#/*                                                                    */
#/*  This source file may be used and distributed without              */
#/*  restriction provided that this copyright statement is not         */
#/*  removed from the file and that any derivative work contains       */
#/*  the original copyright notice and the associated disclaimer.      */
#/*                                                                    */
#/*  This source file is free software; you can redistribute it        */
#/*  and/or modify it under the terms of the GNU Lesser General        */
#/*  Public License as published by the Free Software Foundation;      */
#/*  either version 2.1 of the License, or (at your option) any        */
#/*  later version.                                                    */
#/*                                                                    */
#/*  This source is distributed in the hope that it will be            */
#/*  useful, but WITHOUT ANY WARRANTY; without even the implied        */
#/*  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR           */
#/*  PURPOSE.  See the GNU Lesser General Public License for more      */
#/*  details.                                                          */
#/*                                                                    */
#/*  You should have received a copy of the GNU Lesser General         */
#/*  Public License along with this source; if not, download it        */
#/*  from http://www.opencores.org/lgpl.shtml                          */
#/*                                                                    */
#/**********************************************************************/
 
#  ToDo:
#  parse reg from output bus name
#  parse bus and change pin type to bus
 
use Verilog::Netlist;
 
# Setup options so files can be found
use Verilog::Getopt;
my $opt = new Verilog::Getopt;
$opt->parameter( "+incdir+verilog",
                    "-y","verilog",
               );
 
 
 
 
 
 
 
 
my @files            = ();
 
$SRCFILE            = @ARGV[0];
$outfile            = @ARGV[1];
 
 
 
 
             push @files,  "$SRCFILE";
 
 
 
 
# Prepare netlist
my $nl = new Verilog::Netlist (options => $opt,);
 
foreach $file (@files) {
                        print "Parsing   $file\n";
                        $nl->read_file (filename=>$file);
}
 
 
 
 
 
 
 
# Read in any sub-modules
$nl->link();
$nl->exit_if_error();
 
 
foreach my $mod ($nl->top_modules_sorted) {make_sch ($mod);}
 
 
 
sub make_sch {
        my $mod = shift;
        my $mod_name  = $mod->name;
 
        my $in_count   = 0;
        my $out_count  = 0;
        my $in_length  = 0;
        my $out_length = 0;
 
        my $color =  5;
        my $size  = 10;
 
 
        open(FILE,">${outfile}/${mod_name}.sym") or die "No sym directory";
 
        foreach my $sig ($mod->ports_sorted) {
 
            my $dir       =  $sig->direction;
            my $data_type =  $sig->data_type;
            my $sig_name  =  $sig->name;
            $data_type  =~ s/reg //;
            $data_type  =~ s/reg//;
 
 
            if($data_type)
              {
              $pin_name = "$sig_name"."$data_type";
              if("in" eq  $dir)
                {
                push(@invads,$pin_name);
                $in_count = $in_count+1;
                if( length($pin_name) > $in_length) { $in_length =  length($pin_name)};
                }
              if("out" eq  $dir)
                {
                push(@outvads,$pin_name);
                $out_count = $out_count+1;
                if( length($pin_name) > $out_length){  $out_length =  length($pin_name)            }
                }
 
              if("inout" eq  $dir)
                {
                push(@inoutvads,$pin_name);
                $out_count = $out_count+1;
                if( length($pin_name) > $out_length){  $out_length =  length($pin_name)            }
                }
 
 
 
              }
            else
              {
              $pin_name = $sig_name;
              if("in" eq  $dir)
                {
                push(@inpads,$pin_name);
                $in_count = $in_count+1;
                if( length($pin_name) > $in_length){  $in_length =  length($pin_name)            }
                }
              if("out" eq  $dir)
                {
                push(@outpads,$pin_name);
                $out_count = $out_count+1;
                if( length($pin_name) > $out_length){  $out_length =  length($pin_name)            }
                }
 
              if("inout" eq  $dir)
                {
                push(@inoutpads,$pin_name);
                $out_count = $out_count+1;
                if( length($pin_name) > $out_length){  $out_length =  length($pin_name)            }
                }
 
              };
 
 
        }
 
        my $max_pins;
 
        if($in_count > $out_count) {$max_pins = $in_count ;} else  {$max_pins = $out_count ;}
 
        my $box_h   = ($max_pins * 200) +300;
        my $box_w   = ($in_length +$out_length)*10*$size +400;
        my $out_title = ($in_length +$out_length)*10*$size +600;
        my $out_edg = ($in_length +$out_length)*10*$size +700;
        my $out_pad = ($in_length +$out_length)*10*$size +1000;
        my $title   = $box_h +150;
        my $ref_des = $box_h +350;
 
        printf FILE ("v 20100214 1\n");
        printf FILE ("B 300 0  $box_w $box_h 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1\n");
        printf FILE ("T 400 $title 5 10 1 1 0 0 1 1\ndevice=%s\n", $mod->name);
        printf FILE ("T 400 $ref_des 8 10 1 1 0 0 1 1\n%srefdes=U?\n");
 
        printf  ("%s\n", $mod->name);
 
 
         my $pin_y = 200;
         my $pin_seq = 1;
 
         while( $name =pop(@invads))
          {
          printf FILE ("P 300 $pin_y 0 $pin_y 10 1 1 \n");
          printf FILE ("{\nT 400 $pin_y $color $size 1 1 0 1 1 1\npinnumber=%s\n",$name);
          printf FILE ("T 400 $pin_y $color $size 0 1 0 1 1 1\npinseq=%s\n}\n",$pin_seq);
          $pin_seq = $pin_seq +1;
          $pin_y = $pin_y +200;
          }
 
 
         while( $name =pop(@inpads))
          {
           printf FILE ("P 300 $pin_y 0 $pin_y 4 0 1  \n");
           printf FILE ("{\nT 400 $pin_y $color $size 1 1 0 1 1 1 \npinnumber=%s\n",$name);
           printf FILE ("T 400 $pin_y $color $size 0 1 0 1 1 1 \npinseq=%s\n}\n",$pin_seq);
           $pin_seq = $pin_seq +1;
           $pin_y = $pin_y +200;
          }
 
 
 
         $pin_y = 200;
 
         while( $name =pop(@outvads))
          {
           printf FILE ("P $out_edg $pin_y $out_pad $pin_y 10 1 1\n");
           printf FILE ("{\nT $out_title $pin_y $color  $size 1 1 0 7 1 1 \npinnumber=%s\n",$name);
           printf FILE ("T $out_title $pin_y $color  $size 0 1 0 7 1 1 \npinseq=%s\n}\n",$pin_seq);
           $pin_seq = $pin_seq +1;
           $pin_y = $pin_y +200;
          }
 
 
         while( $name =pop(@outpads))
          {
           printf FILE ("P $out_edg $pin_y $out_pad $pin_y 4 0 1\n");
           printf FILE ("{\nT $out_title $pin_y $color  $size 1 1 0 7 1 1\npinnumber=%s\n",$name);
           printf FILE ("T $out_edg $pin_y $color  $size 0 1 0 7 1 1\npinseq=%s\n}\n",$pin_seq);
           $pin_seq = $pin_seq +1;
           $pin_y = $pin_y +200;
          }
 
 
 
 
         while( $name =pop(@inoutvads))
          {
           printf FILE ("P $out_edg $pin_y $out_pad $pin_y 10 1 1\n");
           printf FILE ("{\nT $out_title $pin_y $color  $size 1 1 0 7 1 1 \npinnumber=%s\n",$name);
           printf FILE ("T $out_title $pin_y $color  $size 0 1 0 7 1 1 \npinseq=%s\n}\n",$pin_seq);
           $pin_seq = $pin_seq +1;
           $pin_y = $pin_y +200;
          }
 
 
         while( $name =pop(@inoutpads))
          {
           printf FILE ("P $out_edg $pin_y $out_pad $pin_y 4 0 1\n");
           printf FILE ("{\nT $out_title $pin_y $color  $size 1 1 0 7 1 1\npinnumber=%s\n",$name);
           printf FILE ("T $out_edg $pin_y $color  $size 0 1 0 7 1 1\npinseq=%s\n}\n",$pin_seq);
           $pin_seq = $pin_seq +1;
           $pin_y = $pin_y +200;
          }
 
 
 
 
 
 
 
 
        foreach my $cell ($mod->cells_sorted) {
            close(FILE);
            make_sch ($cell->submod, $cell->name) if $cell->submod;
        }
    }
 
 
 
 
 
 
 
1;
 
 
 
 
 
 
 

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Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [documentation/] [ver2gedasym] - Blame information for rev 128

Line No.	Rev	Author	Line
1	128	jt_eaton	eval 'exec `which perl` -S $0 ${1+"$@"}'
2			`if 0;`
3
4			`#/**********************************************************************/`
5			`#/* */`
6			`#/* ------- */`
7			`#/* / SOC \ */`
8			`#/* / GEN \ */`
9			`#/* / TOOL \ */`
10			`#/* ============== */`
11			`#/* \| \| */`
12			`#/* \|____________\| */`
13			`#/* */`
14			`#/* convert verilog file(s) to a geda symbol */`
15			`#/* */`
16			`#/* */`
17			`#/* Author(s): */`
18			`#/* - John Eaton, jt_eaton@opencores.org */`
19			`#/* */`
20			`#/**********************************************************************/`
21			`#/* */`
22			`#/* Copyright (C) <2010> */`
23			`#/* */`
24			`#/* This source file may be used and distributed without */`
25			`#/* restriction provided that this copyright statement is not */`
26			`#/* removed from the file and that any derivative work contains */`
27			`#/* the original copyright notice and the associated disclaimer. */`
28			`#/* */`
29			`#/* This source file is free software; you can redistribute it */`
30			`#/* and/or modify it under the terms of the GNU Lesser General */`
31			`#/* Public License as published by the Free Software Foundation; */`
32			`#/* either version 2.1 of the License, or (at your option) any */`
33			`#/* later version. */`
34			`#/* */`
35			`#/* This source is distributed in the hope that it will be */`
36			`#/* useful, but WITHOUT ANY WARRANTY; without even the implied */`
37			`#/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */`
38			`#/* PURPOSE. See the GNU Lesser General Public License for more */`
39			`#/* details. */`
40			`#/* */`
41			`#/* You should have received a copy of the GNU Lesser General */`
42			`#/* Public License along with this source; if not, download it */`
43			`#/* from http://www.opencores.org/lgpl.shtml */`
44			`#/* */`
45			`#/**********************************************************************/`
46
47			`# ToDo:`
48			`# parse reg from output bus name`
49			`# parse bus and change pin type to bus`
50
51			`use Verilog::Netlist;`
52
53			`# Setup options so files can be found`
54			`use Verilog::Getopt;`
55			`my $opt = new Verilog::Getopt;`
56			`$opt->parameter( "+incdir+verilog",`
57			`"-y","verilog",`
58			`);`
59
60
61
62
63
64
65
66
67			`my @files = ();`
68
69			`$SRCFILE = @ARGV[0];`
70			`$outfile = @ARGV[1];`
71
72
73
74
75			`push @files, "$SRCFILE";`
76
77
78
79
80			`# Prepare netlist`
81			`my $nl = new Verilog::Netlist (options => $opt,);`
82
83			`foreach $file (@files) {`
84			`print "Parsing $file\n";`
85			`$nl->read_file (filename=>$file);`
86			`}`
87
88
89
90
91
92
93
94			`# Read in any sub-modules`
95			`$nl->link();`
96			`$nl->exit_if_error();`
97
98
99			`foreach my $mod ($nl->top_modules_sorted) {make_sch ($mod);}`
100
101
102
103			`sub make_sch {`
104			`my $mod = shift;`
105			`my $mod_name = $mod->name;`
106
107			`my $in_count = 0;`
108			`my $out_count = 0;`
109			`my $in_length = 0;`
110			`my $out_length = 0;`
111
112			`my $color = 5;`
113			`my $size = 10;`
114
115
116			`open(FILE,">${outfile}/${mod_name}.sym") or die "No sym directory";`
117
118			`foreach my $sig ($mod->ports_sorted) {`
119
120			`my $dir = $sig->direction;`
121			`my $data_type = $sig->data_type;`
122			`my $sig_name = $sig->name;`
123			`$data_type =~ s/reg //;`
124			`$data_type =~ s/reg//;`
125
126
127			`if($data_type)`
128			`{`
129			`$pin_name = "$sig_name"."$data_type";`
130			`if("in" eq $dir)`
131			`{`
132			`push(@invads,$pin_name);`
133			`$in_count = $in_count+1;`
134			`if( length($pin_name) > $in_length) { $in_length = length($pin_name)};`
135			`}`
136			`if("out" eq $dir)`
137			`{`
138			`push(@outvads,$pin_name);`
139			`$out_count = $out_count+1;`
140			`if( length($pin_name) > $out_length){ $out_length = length($pin_name) }`
141			`}`
142
143			`if("inout" eq $dir)`
144			`{`
145			`push(@inoutvads,$pin_name);`
146			`$out_count = $out_count+1;`
147			`if( length($pin_name) > $out_length){ $out_length = length($pin_name) }`
148			`}`
149
150
151
152			`}`
153			`else`
154			`{`
155			`$pin_name = $sig_name;`
156			`if("in" eq $dir)`
157			`{`
158			`push(@inpads,$pin_name);`
159			`$in_count = $in_count+1;`
160			`if( length($pin_name) > $in_length){ $in_length = length($pin_name) }`
161			`}`
162			`if("out" eq $dir)`
163			`{`
164			`push(@outpads,$pin_name);`
165			`$out_count = $out_count+1;`
166			`if( length($pin_name) > $out_length){ $out_length = length($pin_name) }`
167			`}`
168
169			`if("inout" eq $dir)`
170			`{`
171			`push(@inoutpads,$pin_name);`
172			`$out_count = $out_count+1;`
173			`if( length($pin_name) > $out_length){ $out_length = length($pin_name) }`
174			`}`
175
176			`};`
177
178
179			`}`
180
181			`my $max_pins;`
182
183			`if($in_count > $out_count) {$max_pins = $in_count ;} else {$max_pins = $out_count ;}`
184
185			`my $box_h = ($max_pins * 200) +300;`
186			`my $box_w = ($in_length +$out_length)10$size +400;`
187			`my $out_title = ($in_length +$out_length)10$size +600;`
188			`my $out_edg = ($in_length +$out_length)10$size +700;`
189			`my $out_pad = ($in_length +$out_length)10$size +1000;`
190			`my $title = $box_h +150;`
191			`my $ref_des = $box_h +350;`
192
193			`printf FILE ("v 20100214 1\n");`
194			`printf FILE ("B 300 0 $box_w $box_h 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1\n");`
195			`printf FILE ("T 400 $title 5 10 1 1 0 0 1 1\ndevice=%s\n", $mod->name);`
196			`printf FILE ("T 400 $ref_des 8 10 1 1 0 0 1 1\n%srefdes=U?\n");`
197
198			`printf ("%s\n", $mod->name);`
199
200
201			`my $pin_y = 200;`
202			`my $pin_seq = 1;`
203
204			`while( $name =pop(@invads))`
205			`{`
206			`printf FILE ("P 300 $pin_y 0 $pin_y 10 1 1 \n");`
207			`printf FILE ("{\nT 400 $pin_y $color $size 1 1 0 1 1 1\npinnumber=%s\n",$name);`
208			`printf FILE ("T 400 $pin_y $color $size 0 1 0 1 1 1\npinseq=%s\n}\n",$pin_seq);`
209			`$pin_seq = $pin_seq +1;`
210			`$pin_y = $pin_y +200;`
211			`}`
212
213
214			`while( $name =pop(@inpads))`
215			`{`
216			`printf FILE ("P 300 $pin_y 0 $pin_y 4 0 1 \n");`
217			`printf FILE ("{\nT 400 $pin_y $color $size 1 1 0 1 1 1 \npinnumber=%s\n",$name);`
218			`printf FILE ("T 400 $pin_y $color $size 0 1 0 1 1 1 \npinseq=%s\n}\n",$pin_seq);`
219			`$pin_seq = $pin_seq +1;`
220			`$pin_y = $pin_y +200;`
221			`}`
222
223
224
225			`$pin_y = 200;`
226
227			`while( $name =pop(@outvads))`
228			`{`
229			`printf FILE ("P $out_edg $pin_y $out_pad $pin_y 10 1 1\n");`
230			`printf FILE ("{\nT $out_title $pin_y $color $size 1 1 0 7 1 1 \npinnumber=%s\n",$name);`
231			`printf FILE ("T $out_title $pin_y $color $size 0 1 0 7 1 1 \npinseq=%s\n}\n",$pin_seq);`
232			`$pin_seq = $pin_seq +1;`
233			`$pin_y = $pin_y +200;`
234			`}`
235
236
237			`while( $name =pop(@outpads))`
238			`{`
239			`printf FILE ("P $out_edg $pin_y $out_pad $pin_y 4 0 1\n");`
240			`printf FILE ("{\nT $out_title $pin_y $color $size 1 1 0 7 1 1\npinnumber=%s\n",$name);`
241			`printf FILE ("T $out_edg $pin_y $color $size 0 1 0 7 1 1\npinseq=%s\n}\n",$pin_seq);`
242			`$pin_seq = $pin_seq +1;`
243			`$pin_y = $pin_y +200;`
244			`}`
245
246
247
248
249			`while( $name =pop(@inoutvads))`
250			`{`
251			`printf FILE ("P $out_edg $pin_y $out_pad $pin_y 10 1 1\n");`
252			`printf FILE ("{\nT $out_title $pin_y $color $size 1 1 0 7 1 1 \npinnumber=%s\n",$name);`
253			`printf FILE ("T $out_title $pin_y $color $size 0 1 0 7 1 1 \npinseq=%s\n}\n",$pin_seq);`
254			`$pin_seq = $pin_seq +1;`
255			`$pin_y = $pin_y +200;`
256			`}`
257
258
259			`while( $name =pop(@inoutpads))`
260			`{`
261			`printf FILE ("P $out_edg $pin_y $out_pad $pin_y 4 0 1\n");`
262			`printf FILE ("{\nT $out_title $pin_y $color $size 1 1 0 7 1 1\npinnumber=%s\n",$name);`
263			`printf FILE ("T $out_edg $pin_y $color $size 0 1 0 7 1 1\npinseq=%s\n}\n",$pin_seq);`
264			`$pin_seq = $pin_seq +1;`
265			`$pin_y = $pin_y +200;`
266			`}`
267
268
269
270
271
272
273
274
275			`foreach my $cell ($mod->cells_sorted) {`
276			`close(FILE);`
277			`make_sch ($cell->submod, $cell->name) if $cell->submod;`
278			`}`
279			`}`
280
281
282
283
284
285
286
287			`1;`
288
289
290
291
292
293
294