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[/] [sockit_owm/] [trunk/] [hdl/] [wishbone2bus.v] - Blame information for rev 3

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1 3 iztok
module wishbone2bus #(
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  parameter AW =  2,              // address width
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  parameter DW = 32,              // data    width
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  parameter SW = DW/8             // select  width
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)(
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  // Wishbone master port
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  input  wire          wb_cyc,    // cycle
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  input  wire          wb_stb,    // strobe
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  input  wire          wb_we,     // write enable
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  input  wire [AW-1:0] wb_adr,    // address
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  input  wire [SW-1:0] wb_sel,    // byte select
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  input  wire [DW-1:0] wb_dat_w,  // write data
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  output wire [DW-1:0] wb_dat_r,  // read  data
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  output wire          wb_ack,    // acknowledge
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  output wire          wb_err,    // error
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  output wire          wb_rty,    // retry
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  // Avalon slave port
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  output wire          bus_wen,   // write enable
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  output wire          bus_ren,   // read  enable
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  output wire [AW-1:0] bus_adr,   // address
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  output wire [DW-1:0] bus_wdt,   // write data
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  input  wire [DW-1:0] bus_rdt    // read  data
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);
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// bus write and read enable
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assign bus_wen = wb_cyc & wb_stb &  wb_we;
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assign bus_ren = wb_cyc & wb_stb & ~wb_we;
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// address
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assign bus_adr = wb_adr;
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// write data
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assign bus_wdt = wb_dat_w;
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// read data
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assign wb_dat_r = bus_rdt;
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// error if not full width access else acknowledge
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assign wb_ack =  &wb_sel;
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assign wb_err = ~&wb_sel;
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assign wb_rty =     1'b0;
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endmodule

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